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Showing results
SystemVerilog 1 Updated Apr 1, 2025

AI-Driven Verilator Gap Checker (langgraph-based)

Python 1 Updated Oct 13, 2025

Intelligent automation and multi-agent orchestration for Claude Code

Python 18,377 2,050 Updated Oct 19, 2025

Enables access from cocotb/Pyuvm to SystemVerilog Verification IP. Besides re-usable code, this repo contains a simple example implementation

Python 2 1 Updated Nov 20, 2024

Functional verification project for the CORE-V family of RISC-V cores.

Assembly 1 Updated Feb 24, 2025

A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology

109 93 Updated Mar 18, 2014

Complete UVM TestBench For Verification Of D Flip Flop

SystemVerilog 6 5 Updated Jun 16, 2021

A complete UVM TB for verification of single port 64KB RAM

SystemVerilog 15 8 Updated Apr 16, 2021

Functional verification project for the CORE-V family of RISC-V cores.

Assembly 603 259 Updated Oct 16, 2025

PlanV CI System for testing Verilator-Features

SystemVerilog 1 Updated Aug 5, 2025

Verilator open-source SystemVerilog simulator and lint system

C++ 3,122 709 Updated Oct 18, 2025

Verilator open-source SystemVerilog simulator and lint system

C++ 1 Updated Oct 12, 2025
C++ 1 Updated Jul 1, 2024

The UVM written in Python

Python 466 91 Updated Oct 18, 2025

Toy project to practice SystemC skills

Makefile 1 Updated Apr 6, 2024
点击 这是indexloc提供的php浏览器服务,不要输入任何密码和下载