This project implements a hardware-accelerated SHA-256 cryptographic hash function using Verilog HDL, designed for FPGA deployment. The core is wrapped with an AXI4-Lite slave interface.

┌─────────────────────────────────────────────────────────┐
│                  AXI4-Lite Master                       │
│                  (ARM Processor)                        │
└──────────────────────┬──────────────────────────────────┘
                       │ AXI4-Lite Bus
┌──────────────────────▼──────────────────────────────────┐
│         myip_slave_lite_v1_0_S00_AXI                    │
│         (AXI Wrapper Module)                            │
│  ┌────────────────────────────────────────────────┐    │
│  │  Control Registers (slv_reg0 - slv_reg69)     │    │
│  │  • Input Data: reg0-reg15 (512 bits)          │    │
│  │  • Hash Output: reg16-reg23 (256 bits)        │    │
│  │  • Control: reg24 (init signal)               │    │
│  │  • Status: reg25 (hash_ready)                 │    │
│  └───────────────────┬────────────────────────────┘    │
└────────────────────────┼────────────────────────────────┘
                         │
┌────────────────────────▼────────────────────────────────┐
│         secure_hash_algorithm                           │
│         (SHA-256 Core)                                  │
│  ┌──────────────────────────────────────────────┐      │
│  │  State Machine: IDLE → BUSY → DONE          │      │
│  └──────────────────────────────────────────────┘      │
│  ┌──────────────┐  ┌──────────────┐  ┌─────────┐      │
│  │ Scheduling   │  │  K-Values    │  │ Hash    │      │
│  │ Unit         │  │  ROM         │  │ Engine  │      │
│  └──────────────┘  └──────────────┘  └─────────┘      │
└─────────────────────────────────────────────────────────┘

1. Input: 512-bit data block written to registers 0-15
2. Control: Init signal triggers hash computation
3. Processing: 64 rounds of SHA-256 algorithm
4. Output: 256-bit hash result stored in registers 16-23
5. Status: Ready flag set in register 25

File: axi_wrapper.v

AXI4-Lite slave interface wrapper that handles bus transactions and register management.

Key Features:

• Write state machine with Idle, Waddr, Wdata states
• Read state machine with Idle, Raddr, Rdata states
• 70 × 32-bit slave registers
• Byte-enable support via write strobes
• Instantiates SHA-256 core

File: sha256_main.v

Core SHA-256 hashing engine implementing the complete algorithm.

Features:

• Initial hash values (H0-H7)
• 64-round computation
• State machine: IDLE, BUSY, DONE
• Working variables: a, b, c, d, e, f, g, h
• Integration with scheduling unit and K-values ROM

Functions:

• right_rotate: Circular right rotation
• sigma0, sigma1: SHA-256 Σ functions
• choice: Ch(x, y, z) function
• majority: Maj(x, y, z) function

File: scheduling_unit.v

Message schedule generator that expands the 512-bit input block into 64 × 32-bit words.

Operation:

• First 16 words: Direct from input (W[0] to W[15])
• Remaining 48 words: Computed using σ0 and σ1 functions
• Formula: W[t] = σ1(W[t-2]) + W[t-7] + σ0(W[t-15]) + W[t-16]

Functions:

• sigma0: σ0(x) = ROTR⁷(x) ⊕ ROTR¹⁸(x) ⊕ SHR³(x)
• sigma1: σ1(x) = ROTR¹⁷(x) ⊕ ROTR¹⁹(x) ⊕ SHR¹⁰(x)

File: k_values.v

ROM module containing the 64 constant values (K0-K63) used in SHA-256.

Implementation:

• Combinational logic with case statement
• 6-bit index input
• 32-bit constant output
• Values derived from cube roots of first 64 primes

• Multi-block message support
• DMA interface
• Interrupt generation on completion
• HMAC-SHA256 implementation
• Power optimization
• Support for SHA-224, SHA-384, SHA-512
• Padding logic in hardware
• Performance counters