A smithy for rusty wayland compositors

Empowering everyone to build reliable and efficient software.

Linux linker for x86 and x86-64

BSD-licensed Yamaha FM sound cores (OPM, OPN, OPL, and others)

Open-source E-ink monitor. Mirror of https://gitlab.com/zephray/glider

The open-source Zynq 7000 BSP generator for openXC7

A 5$ Xilinx ZYNQ development board.

Fully documented and annotated source code for Elite on the Commodore 64

A tiny C header-only risc-v emulator.

libpulp enables live patching in user space applications.

A robust, efficient, low-latency speech-to-text library with advanced voice activity detection, wake word activation and instant transcription.

iCESugar series FPGA dev board

A minimum configuration for Neovim targeting SystemVerilog that provides configuration for plugin management, a language server, tree-sitter, and linting

Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats

SystemVerilog synthesis tool

A simple RISC V core for teaching

Online demonstration for DigitalJS

Improve keyboard comfort and usability with advanced customization

sensible.vim: Defaults everyone can agree on

Bitbanged DVI on the RP2040 Microcontroller

Cross-platform Rust rewrite of the GNU coreutils

fugitive.vim: A Git wrapper so awesome, it should be illegal

Verilog library for ASIC and FPGA designers

🔍 A Hex Editor for Reverse Engineers, Programmers and people who value their retinas when working at 3 AM.

Port Allwinner xradio driver to mainline Linux.

NixOS port for OrangePi R1 Plus. WIP

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform