An integrated power, area, and timing modeling framework for multicore and manycore architectures

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Convolutional accelerator kernel, target ASIC & FPGA

DLAFNet: Direct LiDAR-Aerial Fusion Network for Semantic Segmentation of 2D Aerial Image and 3D LiDAR Point Cloud

A simple RV32IM-based SoC (modified version of tinyriscv)

IC implementation of TPU

AI Chip project

FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Daughter card for Xilinx VCU128 adding a SD card socket and a JTAG header

【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器

AXI总线连接器

Open Overleaf/ShareLaTex projects in vscode, with full collaboration support.

Here are some Ventus OpenCL testcases

Official repository of 'Visual-RFT: Visual Reinforcement Fine-Tuning' & 'Visual-ARFT: Visual Agentic Reinforcement Fine-Tuning'’

An Open Source Machine Learning Framework for Everyone

General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。

C语言版的stream2

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

FashionMNIST Dataset train and test by mlp

use vitis vision library to complete resize and sobel image processing

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL