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Writing Bugs
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Writing Bugs

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@SEU-MSLab

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ataraxiaz/README.md

💫 About Me:

🔭 I’m currently working on FPGA hardware and software co-design
👯 I’m looking to collaborate on anything about FPGA
🌱 I’m currently learning Linux, Chisel, SystemVerilog
💬 Ask me about anything related to FPGA

💻 Tech Stack:

Python C++ Scala PyTorch NumPy Pandas LINUX Trello

📊 GitHub Stats:




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  1. SEU-MSLab/MP SEU-MSLab/MP Public

    The software and hardware implementation of Memory Polynomial algorithm

    SystemVerilog 8 3

  2. SEU-MSLab/PRVTDNN SEU-MSLab/PRVTDNN Public

    The Chisel design of Polyphase Real-Value Time-Delay Neural Network (PRVTDNN).

    Scala 1 1

点击 这是indexloc提供的php浏览器服务,不要输入任何密码和下载