:)
Student studing Electronic and Information Engineering at Imperial College London
Stars
Lecture notes on communication and signal processing related topics. For archival/reference purposes only.
Generic Register Interface (contains various adapters)
Simple single-port AXI memory interface
RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Automatic CPU speed & power optimizer for Linux
TFHE: Fast Fully Homomorphic Encryption Library over the Torus
Arch Linux post-installation setup and config scripts