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Jianwei Jiang 0001
Person information
- affiliation: University of Chinese Academy of Sciences, Beijing, China
Other persons with the same name
- Jianwei Jiang 0002
— School of Software, Shanghai Jiao Tong University, Shanghai, China
- Jianwei Jiang 0003 (aka: Jianwei Patrick Jiang) — University of Canterbury, Christchurch, New Zealand
- Jianwei Jiang 0004 — Hebei University of Economics and Business, Shijiazhuang, Hebei, China
- Jianwei Jiang 0005 — Shanghai Maritime University, College of Information Engineering, China
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Journal Articles
- 2022
- [j7]Zhongyang Liu
A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design. IEEE Trans. Very Large Scale Integr. Syst. 30(12): 1867-1877 (2022) - 2020
- [j6]Wenyi Zhu
A Wide-Range-Supply-Voltage Sense Amplifier Circuit for Embedded Flash Memory. IEEE Trans. Circuits Syst. II Express Briefs 67-II(8): 1454-1458 (2020) - 2019
- [j5]Wenyi Zhu, Jianwei Jiang, Dianpeng Lin, Jun Xiao, Guangjun Yang, Xiaoyun Li, Shichang Zou:
A charge pump system with new regulation and clocking scheme. IEICE Electron. Express 16(4): 20190005 (2019) - [j4]Jianwei Jiang
Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 967-977 (2019) - 2018
- [j3]Dianpeng Lin, Yiran Xu, Xiaonian Liu, Wenyi Zhu, Lihua Dai, Mengying Zhang, Xiaoyun Li, Xin Xie, Jianwei Jiang, Huilong Zhu, Zhengxuan Zhang, Shichang Zou:
A novel highly reliable and low-power radiation hardened SRAM bit-cell design. IEICE Electron. Express 15(3): 20171129 (2018) - [j2]Dianpeng Lin, Yiran Xu, Xiaoyun Li, Xin Xie, Jianwei Jiang, Jiangchuan Ren, Huilong Zhu, Zhengxuan Zhang, Shichang Zou:
A novel SEU tolerant memory cell for space applications. IEICE Electron. Express 15(17): 20180656 (2018) - [j1]Dianpeng Lin, Yiran Xu, Xiaoyun Li, Xin Xie, Jianwei Jiang, Jiangchuan Ren, Huilong Zhu, Zhengxuan Zhang, Shichang Zou:
A novel self-recoverable and triple nodes upset resilience DICE latch. IEICE Electron. Express 15(19): 20180753 (2018)
Conference and Workshop Papers
- 2019
- [c1]Jianwei Jiang, Dianpeng Lin, Jun Xiao, Shichang Zou:
Soft-Error-Tolerant Ultralow-Leakage 12T SRAM Bitcell Design. ICICDT 2019: 1-2
Coauthor Index
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