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IET Computers & Digital Techniques, Volume 4
Volume 4, Number 1, January 2010
- Zhen Chen, J. Feng, Dong Xiang, Boxue Yin:
Scan chain configuration based X-filling for low power and high quality testing. 1-13 - Máire O'Neill, Matthew J. B. Robshaw:
Low-cost digital signature architecture suitable for radio frequency identification tags. 14-26 - Jih-Ching Chiu, Ta-Li Yeh:
IRES: An integrated software and hardware interface framework for reconfigurable embedded system. 27-37 - Michael Higgins, Ciaran MacNamee, Brendan Mullane
:
Design and implementation challenges for adoption of the IEEE 1500 standard. 38-49 - (Withdrawn) Scheme to minimise short effects of single-event upsets in triple-modular redundancy. 50-55
- Seyed Ebrahim Esmaeili
Skew compensation in energy recovery clock distribution networks. 56-72 - Harikrishna Samala, Aravind Dasu:
Methodology to derive resource aware context adaptable architectures for FPGAs. 73-88
Volume 4, Number 2, March 2010
- Irith Pomeranz, Sudhakar M. Reddy:
Diagnosis of path delay faults based on low-coverage tests. 89-103 - Paolo Bernardi
Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug. 104-113 - Ryan N. Rakvic, José González, Qiong Cai, Pedro Chaparro, Grigorios Magklis, Antonio González
Energy efficiency via thread fusion and value reuse. 114-125 - Arvind Sudarsanam, Robert Collier Barnes, J. Carver, Ramachandra Kallam, Aravind Dasu:
Dynamically reconfigurable systolic array accelerators: A case study with extended Kalman filter and discrete wavelet transform algorithms. 126-142 - Shervin Vakili, Sied Mehdi Fakhraie, Siamak Mohammadi
Evolvable multi-processor: A novel MPSoC architecture with evolvable task decomposition and scheduling. 143-156
Volume 4, Number 3, May 2010
- Udo Kebschull, Marco Platzner
Selected papers from the 18th International Conference on Field Programmable Logic and Applications (FPL 2008) [Editorial]. 157-158 - Matthew Shelburne, Cameron D. Patterson, Peter Athanas, Mark Jones, Brian S. Martin, Ryan Fong:
MetaWire: Using FPGA configuration circuitry to emulate a network-on-chip. 159-169 - Kristofer Vorwerk, Andrew A. Kennings, Val Pevzner, Arun Kundu, Madhu Raman, Julien Dunoyer, Yaun-shung Hsu:
Power minimisation during field programmable gate array placement. 170-183 - Bharat Sukhwani, Martin C. Herbordt:
FPGA acceleration of rigid-molecule docking codes. 184-195 - Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung:
Fault tolerance and reliability in field-programmable gate arrays. 196-210 - Yoann Guillemenet, Lionel Torres, Gilles Sassatelli:
Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories. 211-226 - B. A. Al Jassani, Neil Urquhart, A. E. A. Almaini:
Manipulation and optimisation techniques for Boolean logic. 227-239 - Aissa Melouki, Saket Srivastava
Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. 240-250 - Bo Fu, Paul Ampadu:
Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects. 251-261
Volume 4, Number 4, July 2010
- Jimson Mathew, Abusaleh M. Jabir, Ashutosh Kumar Singh
A Galois field-based logic synthesis with testability. 263-273 - Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey:
Test pattern generation for droop faults. 274-284 - Meng-Hsueh Chiang, Yi-Bo Liao, Jun-Tin Lin, Wei-Chou Hsu, Chu Yu, Pei-Chia Chiang, Y.-Y. Hsu, W.-H. Liu, Shyh-Shyuan Sheu, Keng-Li Su, Ming-Jer Kao, Ming-Jinn Tsai:
Low power design of phase-change memory based on a comprehensive model. 285-292 - Jong-Myon Kim, Sung Woo Chung, Cheol Hong Kim:
Energy-aware instruction cache design using small trace cache. 293-305 - Feng Liu, Qingping Tan, Gang Chen, Xiaoyu Song, Otmane Aït Mohamed, Ming Gu:
Field programmable gate array prototyping of end-around carry parallel prefix tree architectures. 306-316 - Wang-Dauh Tseng, Lung-Jen Lee, Rung-Bin Lin:
Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction. 317-324 - Qian Ding, Yu Wang
Output remapping technique for critical paths soft-error rate reduction. 325-333 - Abdelhafid Bouhraoua:
Design feasibility study for a 500 Gbits/s advanced encryption standard cipher/decipher engine. 334-348
Volume 4, Number 5, September 2010
- Liang Lu, John V. McCanny, Sakir Sezer:
Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding. 349-364 - Irith Pomeranz, Sudhakar M. Reddy:
Static test compaction for diagnostic test sets of full-scan circuits. 365-373 - Ming-che Lai, Lei Gao, Zhiying Wang:
Exploration and implementation of a highly efficient processor element for multimedia and signal processing domains. 374-387 - Debasri Saha, Susmita Sur-Kolay:
Robust intellectual property protection of VLSI physical design. 388-399 - J. Choi, H. Cha:
System-level power management for system-on-a-chip -based mobile devices. 400-409 - Hossein Karimiyan, Sayed Masoud Sayedi, Hossein Saidi
Low-power dual-edge triggered state-retention scan flip-flop. 410-419 - X. She, N. Li:
Low-overhead single-event upset hardened latch using programmable resistance cells. 420-427 - Hafizur Rahaman
Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability. 428-437
Volume 4, Number 6, November 2010
- Santanu Kumar Dash
Instruction cache tuning for embedded multitasking applications. 439-457 - Kahraman D. Akdemir, Berk Sunar:
Generic approach for hardening state machines against strong adversaries. 458-470 - Ahmed K. Al-Sulaifanie, Arash Ahmadi
Very large scale integration architecture for integer wavelet transform. 471-483 - Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin:
On-chip memory space partitioning for chip multiprocessors using polyhedral algebra. 484-498 - Seyed Ebrahim Esmaeili
Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks. 499-514 - David O'Sullivan, Donal Heffernan:
VHDL architecture for IEC 61499 function blocks. 515-524
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