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FPT 2006: Bangkok, Thailand
- George A. Constantinides, Wai-Kei Mak, Phaophak Sirisuk, Theerayod Wiangtong:
2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, December 13-15, 2006. IEEE 2006, ISBN 0-7803-9728-2
Keynotes
- Jonathan Rose:
Invited Keynote 1: Closing the gap between FPGAs and ASICs. - Geoff Hall:
Invited Keynote 2: Applications of programmable logic in modern particle physics experiments.
Architecture I
- Peter Jamieson, Jonathan Rose:
Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters. 1-8 - Sebastian Lange, Martin Middendorf:
Granularity aspects for the design of multi-level reconfigurable architectures. 9-16 - Masakazu Hioki
, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Evaluation of granularity on threshold voltage control in flex power FPGA. 17-24
Applications I
- Jinbo Xu, Yong Dou:
Robust and real-time automatic target recognition using partial hausdorff distance measure on reconfigurable hardware. 25-32 - Dong-U Lee, Ray C. C. Cheung
Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation. 33-40 - Dominique Lavenier, Xinchun Liu, Gilles Georges:
Seed-based genomic sequence comparison using a FPGA/FLASH accelerator. 41-48 - Samuel Bayliss, Christos-Savvas Bouganis
An FPGA implementation of the simplex algorithm. 49-56
Tools I
- Xuegong Zhou, Ying Wang, XunZhang Huang, Chenglian Peng:
On-line scheduling of real-time tasks for reconfigurable computing system. 57-64 - Wu Jigang, Thambipillai Srikanthan, Tao Jiao:
Efficient algorithm for functional scheduling in hardware/software co-design. 65-72 - Y. Y. Leow, C. Y. Ng, Weng-Fai Wong
Generating hardware from OpenMP programs. 73-80
Architecture I
- Stamatis Vassiliadis, Ioannis Sourdis:
Reconfigurable FLUX networks. 81-88 - Edmund Lee, Guy Lemieux, Shahriar Mirabbasi:
Interconnect driver design for long wires in field-programmable gate arrays. 89-96 - N. Pete Sedcole, Peter Y. K. Cheung:
Within-die delay variability in 90nm FPGAs and beyond. 97-104 - Dmitrij Kissler, Frank Hannig
A highly parameterizable parallel processor array architecture. 105-112
Applications II
- Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt, Vincent Nollet:
Optimizing the critical loop in the H.264/AVC CABAC decoder. 113-118 - João Bispo
Regular expression matching for reconfigurable packet inspection. 119-126 - Miguel A. Sánchez Marcos, Mario Garrido
Automated design space exploration of FPGA-based FFT architectures based on area and power estimation. 127-134 - Ning Ge
Sigma-delta based clock recovery using on-chip PLL in FPGA. 135-140
Memory
- Stephan Wong, Filipa Duarte, Stamatis Vassiliadis:
A hardware cache memcpy accelerator. 141-148 - Ralf Laue, Sorin A. Huss:
A novel memory architecture for elliptic curve cryptography with parallel modular multipliers. 149-156 - Seth Young, Arvind Sudarsanam, Aravind Dasu, Thomas Hauser
Memory support design for LU decomposition on the starbridge hyper-computer. 157-164
Applications III
- Brian M. H. Li, Philip Heng Wai Leong
FPGA-based MSB-first bit-serial variable block size motion estimation processor. 165-172 - Chang Shu, Soonhak Kwon, Kris Gaj:
FPGA accelerated tate pairing based cryptosystems over binary fields. 173-180 - Maria E. Angelopoulou, Konstantinos Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos:
A comparison of 2-D discrete wavelet transform computation schedules on FPGAs. 181-188
Tools II
- David Grant, Guy Lemieux:
Perturber: semi-synthetic circuit generation using ancestor control for testing incremental place and route. 189-196 - Miljan Vuletic, Paolo Ienne, Christopher Claus, Walter Stechele:
Multithreaded virtual-memory-enabled reconfigurable hardware accelerators. 197-204 - Daniel Ziener
FPGA core watermarking based on power signature analysis. 205-212
Applications IV
- Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins:
FPGA acceleration of the tate pairing in characteristic 2. 213-220 - David de Andrés, Juan-Carlos Ruiz-Garcia
FADES: a fault emulation tool for fast dependability assessment. 221-228 - Phillip H. Jones, Young H. Cho, John W. Lockwood:
An adaptive frequency control method using thermal feedback for reconfigurable hardware applications. 229-236
Poster Session
- Jacobo Álvarez
FPGA implementation of a fuzzy controller for automobile DC-DC converters. 237-240 - Nathalie Bochard, Alain Aubert, Virginie Fresse:
An adaptive and predictive architecture for parameterised PIV algorithms. 241-244 - Zahid Khan, Tughrul Arslan:
A real time programmable encoder for low density parity check code targeting a reconfigurable instruction cell architecture. 245-248 - Fabian Vargas, Leonardo Picolli, Antonio A. de Alecrim Jr., Marlon Moraes, Marcio Gama:
Summarizing a time-sensitive control-flow checking monitoring for multitask systems-on-chip. 249-252 - Nathalie Chan King Choy, Steven J. E. Wilton:
Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs. 253-256 - Peter J. Green, Desmond P. Taylor:
Implementation of a real-time multiple input multiple output channel estimator on the smart antenna software radio test system platform using the Xilinx Virtex 2 Pro Field Programmable Gate Array. 257-260 - Siew Kei Lam
Efficient management of custom instructions for run-time reconfigurable instruction set processors. 261-264 - Judith Liu-Jimenez, Raul Sánchez-Reillo
FPGA implementation for an iris biometric processor. 265-268 - Shin'ichi Wakabayashi, Yoshihiro Kimura, Shinobu Nagayama:
FPGA implementation of tabu search for the quadratic assignment problem. 269-272 - Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt
Minimizing peak power for application chains on architectures with partial dynamic reconfiguration. 273-276 - David A. Kearney, John Hopf:
Hardware join Java: a unified hardware/software language for dynamic partial runtime reconfigurable computing applications. 277-280 - Yiqun Zhu, Barrie Hayes-Gill, Steve Morgan, Nguyen C. Hoang:
An FPGA based generic prototyping platform employed in a CMOS laser Doppler blood flow camera. 281-284 - Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, Hideharu Amano:
An adaptive Viterbi decoder on the dynamically reconfigurable processor. 285-288 - Altaf Abdul Gaffar, Jonathan A. Clarke
PowerBit - power aware arithmetic bit-width optimization. 289-292 - Vincenzo Rana
Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology. 293-296 - Wen-Chih Kan, Gerald E. Sobelman:
Hardware channel model for ultra wideband systems. 297-300 - Narayan Subramanian, Rajarshee P. Bharadwaj, Dinesh Bhatia
A leakage aware design methodology for power-gated programmable architectures. 301-304 - Dan Cyca, Laurence E. Turner:
A C compiler for implementing FPGA based bit-serial DSP systems. 305-308 - Grant B. Wigley, David A. Kearney:
Performance evaluations of ReconfigME. 309-312 - Francisco-Javier Veredas, Hans-Jörg Pfleiderer:
Power estimation of a LUT-based MPGA. 313-316 - Fritz Mayer-Lindenberg, Valerij Beller:
An FPGA-based floating-point processor array supporting a high-precision dot product. 317-320 - Shannon Koh, Oliver Diessel
Communications infrastructure generation for modular FPGA reconfiguration. 321-324 - Abdulrahman Hanoun, Wael Adi, Friedrich Mayer-Lindenberg, Bassel Soudan
Fuzzy modular multiplication architecture and low complexity IPR-protection for FPGA technology. 325-328 - Takashi Kawanami, Masakazu Hioki
Optimal set of body bias voltages for an FPGA with field-programmable Vth components. 329-332 - Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung:
The cost of data dependence in motion vector estimation for reconfigurable platforms. 333-336 - Haohuan Fu, Oskar Mencer, Wayne Luk:
Comparing floating-point and logarithmic number representations for reconfigurable acceleration. 337-340 - Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Dynamically reconfigurable protocol transducer. 341-344 - Christian Plessl
Optimal temporal partitioning based on slowdown and retiming. 345-348 - Altaf Abdul Gaffar, Jonathan A. Clarke
Modeling of glitch effects in FPGA based arithmetic circuits. 349-352 - Tobias Oppold, Sven Eisenhardt, Wolfgang Rosenstiel:
Design and validation of execution schemes for dynamically reconfigurable architectures. 353-356 - Nathaniel Couture, Kenneth B. Kent
Periodic licensing of FPGA based intellectual property. 357-360 - Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani:
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os. 361-364 - Christos-Savvas Bouganis
A statistical framework for dimensionality reduction implementation in FPGAs. 365-368 - Guilherme Luiz Moritz
Hardalign: a parallel pairwise alignment hardware application. 369-372 - Bradley D. Christiansen, Yong C. Kim, Robert W. Bennington, Christopher J. Ristich:
Decoy circuits for FPGA design protection. 373-376 - David B. Thomas, Jacob A. Bower, Wayne Luk:
Hardware architectures for Monte-Carlo based financial simulations. 377-380 - Griselda Saldaña
Customizable FPGA-based architecture for video applications in real time. 381-384 - Chia-Tien Dan Lo, Yi-Gang Tai, Kleanthis Psarris, Wen-Jyi Hwang:
Super fast hardware string matching. 385-388
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