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"A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor."

Takashi Okuda et al. (2000)

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DOI: 10.1109/4.859504

access: closed

type: Journal Article

metadata version: 2022-04-08

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  - https://dblp.org/rec/journals/jssc/OkudaNSNM00
Takashi Okuda, Isao Naritake, Tadahiko Sugibayashi, Yuji Nakajima, Tatsunori Murotani:
A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor. IEEE J. Solid State Circuits 35(8): 1153-1158 (2000)

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