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John Barth 0001
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- affiliation: IBM Systems and Technology Group, Essex Junction, VT, USA
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2020 – today
- 2025
- [c8]Harold Pilo, John Barth, Kapil Dev Dwivedi, Peter Lee, Vikram Kumar, Prasanna Nalawar, Yogeshbhai Patel, Shailendra Sharad, Shakti Singh:
A 38Mb/mm2 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology. ISSCC 2025: 498-500
2010 – 2019
- 2012
- [c7]Balaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer:
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. ICICDT 2012: 1-4 - [c6]John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver:
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. VLSIC 2012: 110-111 - 2011
- [j10]John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao:
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. IEEE J. Solid State Circuits 46(1): 64-75 (2011) - [c5]Subramanian S. Iyer, Toshiaki Kirihata, John E. Barth Jr.:
Three Dimensional integration - Considerations for memory applications. CICC 2011: 1-7 - 2010
- [c4]John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, Nianzheng Cao:
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. ISSCC 2010: 342-343
2000 – 2009
- 2009
- [j9]Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer:
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. IEEE J. Solid State Circuits 44(4): 1216-1226 (2009) - 2008
- [j8]John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits 43(1): 86-95 (2008) - [c3]Jente B. Kuang, Abraham Mathews, John Barth, Fadi H. Gebara, Tuyet Nguyen, Jeremy D. Schaub, Kevin J. Nowka
, Gary D. Carpenter, Don Plass, Erik Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata:
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM. ESSCIRC 2008: 66-69 - 2007
- [c2]John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC 2007: 486-617 - 2005
- [j7]Subramanian S. Iyer, John E. Barth Jr., Paul C. Parries, James P. Norum, James P. Rice, Lyndon R. Logan, Dennis Hoyniak:
Embedded DRAM: Technology platform for the Blue Gene/L chip. IBM J. Res. Dev. 49(2-3): 333-350 (2005) - [j6]John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. IEEE J. Solid State Circuits 40(1): 213-222 (2005) - 2003
- [j5]Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier:
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE J. Solid State Circuits 38(11): 1974-1980 (2003) - 2002
- [j4]John E. Barth Jr., Jeffrey H. Dreibelbis, Eric A. Nelson, Darren Anand, Gary Pomichter, Peter Jakobsen, Michael R. Nelms, Jeffrey Leach, George M. Belansek:
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering. IBM J. Res. Dev. 46(6): 675-690 (2002) - 2001
- [c1]Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, Michael R. Nelms, Jeffrey Leach, George M. Belansek:
Embedded DRAM built in self test and methodology for test insertion. ITC 2001: 975-984
1990 – 1999
- 1998
- [j3]Jeffrey H. Dreibelbis, John Barth, Howard L. Kalter, Rex Kho:
Processor-based built-in self-test for embedded DRAM. IEEE J. Solid State Circuits 33(11): 1731-1740 (1998) - 1995
- [j2]Wayne F. Ellis, John E. Barth Jr., Sri Divakaruni, Jeffrey H. Dreibelbis, Anatol Furman, Erik L. Hedberg, Hsing-San Lee, Thomas M. Maffitt, Christopher P. Miller, Charles H. Stapper, Howard L. Kalter:
Multipurpose DRAM architecture for optimal power, performance, and product flexibility. IBM J. Res. Dev. 39(1-2): 51-62 (1995) - 1990
- [j1]Howard L. Kalter, Charles H. Stapper, John E. Barth Jr., John DiLorenzo, Charles E. Drake, John A. Fifield, Gordon A. Kelley, Scott C. Lewis, Willem B. van der Hoeven, James A. Yankosky:
A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC. IEEE J. Solid State Circuits 25(5): 1118-1128 (1990)
Coauthor Index
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