2 Problems about VLSI Flow #874
Description
Background work
- Yes, I searched the documentation
- Yes, I searched in the Support (Q&A) section of the Discussions and read the posting guidelines
- Yes, I searched prior issues
- This issue is specific to Hammer, i.e., does not belong in a plugin repository instead
- My report does not contain sensitive info (e.g., PDK information under NDA)
- (If applicable) Yes, I searched the Chipyard documentation
- (If applicable) Yes, I searched the Chipyard mailing list
- (If applicable) Yes, I searched the Chipyard issues
Hammer version and plugin hashes
Chipyard: 1.11.0
firtool: 1.61.0
SBT: 1.6.0
hammer: 1.2.0
vcs: 2022
python: 3.10
gcc: 11.4.0
Ubuntu: 22.04
Other Setup
No response
Current Behavior
Issue 1:
I constructed the conda environment by myself instead of using the Chipyard's. Before I installed hammer-vlsi, I could make clean normally in the director chipyard/vlsi/. But after I installed hammer-vlsi, it couldn't work correctly but just continually make buildfile. The problem (a loop) is shown in the below log:
[<global>] Loading hammer-vlsi libraries and reading settings
[<global>] Loading technology 'hammer.technology.asap7'
[<global>] Key technology.asap7.pdk_install_dir has a type str is not yet implemented
[<global>] Key technology.asap7.stdcell_install_dir has a type str is not yet implemented
[tech] Multi-VT GDS's already created
[tech] ICG LIBs already fixed
Action build config output written to output.json
Running with RISCV=/home/cmj/chipyard/toolchains/riscv-tools
rm -rf /home/cmj/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.SmallBoomConfig/gen-collateral
cd /home/cmj/chipyard && java -cp /home/cmj/chipyard/.classpath_cache/tapeout.jar barstools.tapeout.transforms.GenerateModelStageMain --no-dedup --output-file /home/cmj/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.SmallBoomConfig/chipyard.harness.TestHarness.SmallBoomConfig.sfc --output-annotation-file /home/cmj/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.SmallBoomConfig/chipyard.harness.TestHarness.SmallBoomConfig.sfc.anno.json --target-dir /home/cmj/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.SmallBoomConfig/gen-collateral --input-file /home/cmj/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.SmallBoomConfig/chipyard.harness.TestHarness.SmallBoomConfig.fir --annotation-file /home/cmj/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.SmallBoomConfig/chipyard.harness.TestHarness.SmallBoomConfig.appended.anno.json --log-level error --allow-unrecognized-annotations -X none
But normally, it should be
[<global>] Loading hammer-vlsi libraries and reading settings
[<global>] Loading technology 'hammer.technology.asap7'
[<global>] Key technology.asap7.pdk_install_dir has a type str is not yet implemented
[<global>] Key technology.asap7.stdcell_install_dir has a type str is not yet implemented
[tech] Multi-VT GDS's already created
[tech] ICG LIBs already fixed
Action build config output written to output.json
Running with RISCV=/home/cmj/chipyard/.conda-env/riscv-tools
rm -rf build hammer-vlsi-*.log __pycache__ output.json /home/cmj/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/inputs.yml /home/cmj/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sram_generator-output.json /home/cmj/chipyard/.classpath_cache /home/cmj/chipyard/vlsi/generated-src /home/cmj/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sim-inputs.yml /home/cmj/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sim-debug-inputs.yml /home/cmj/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sim-timing-inputs.yml /home/cmj/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/power-inputs.yml
That is, it should stop after rm -rf ...
What's more, whether I type make sim-rtl or make buildfile, it does get stuck in that loop make buildfile. What's the matter with it? Did I overlook some dependencies?
Issue 2:
make: [/home/cmj/chipyard/common.mk:236: /home/cmj/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/model_module_hierarchy.json] Error 1 (ignored)
Does it affect the whole vlsi flow?
Expected Behavior
Normally and correctly make clean, make syn, etc.
Other Information
No response