Test: chip_sw_sleep_pin_wake
Problem: Passes on VCS, fails on Xcelium

This test goes into infinite loop of never ending raising objections due to inconsistency between parent and child resets here. This will end up generating an alert.

The sync_child_rst and sync_parent_rst are generated by a prim_2sync_flop which adds a random cdc delay first here. If cdc_instrumentation is enabled, we use that random delay to delay the src_data_i. In module rstmgr_cnsty_chk both u_parent_sync and u_child_sync instances gets the same random delay value when simulates with VCS. Hence, both parent and child resets are always in sync (consistent).

In Xcelium, this test fails because we get different cdc delay values for both u_parent_sync and u_child_sync instances. Due to that we fell into inconsistency when we don't expect it here.

There is an article I found helpful which explains why VCS does that for different instances of same modules. By adding the switch suggest in this article (xlrm hier_inst_seed), this test is now able to generate inconsistency b/w parent and child resets.