这是indexloc提供的服务,不要输入任何密码
Skip to content
View vasucp1207's full-sized avatar
🦀
🦀

Organizations

@jotaijs @vicharak-in @fury-lang

Block or report vasucp1207

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Starred repositories

7 stars written in Verilog
Clear filter

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,435 319 Updated Jul 16, 2025
Verilog 1,753 398 Updated Nov 18, 2025

A small, light weight, RISC CPU soft core

Verilog 1,477 175 Updated Aug 9, 2025

An open source GPU based off of the AMD Southern Islands ISA.

Verilog 1,255 255 Updated Aug 18, 2025

RISC-V XV6/Linux SoC, marchID: 0x2b

Verilog 983 68 Updated Nov 14, 2025

Small-scale Tensor Processing Unit built on an FPGA

Verilog 206 27 Updated Aug 4, 2019

A simple 8-bit computer build in Verilog.

Verilog 85 36 Updated Jun 2, 2025