# SAM3S8 UART0

## Universal Asynchronous Receiver Transmitter (UART0) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0x400E0600 | Control Register | UART0_CR | write-only | -
0x400E0604 | Mode Register | UART0_MR | read-write | 0x00000000
0x400E0608 | Interrupt Enable Register | UART0_IER | write-only | -
0x400E060C | Interrupt Disable Register | UART0_IDR | write-only | -
0x400E0610 | Interrupt Mask Register | UART0_IMR | read-only | 0x00000000
0x400E0614 | Status Register | UART0_SR | read-only | -
0x400E0618 | Receive Holding Register | UART0_RHR | read-only | 0x00000000
0x400E061C | Transmit Holding Register | UART0_THR | write-only | -
0x400E0620 | Baud Rate Generator Register | UART0_BRGR | read-write | 0x00000000
0x400E0700 | Receive Pointer Register | UART0_RPR | read-write | 0x00000000
0x400E0704 | Receive Counter Register | UART0_RCR | read-write | 0x00000000
0x400E0708 | Transmit Pointer Register | UART0_TPR | read-write | 0x00000000
0x400E070C | Transmit Counter Register | UART0_TCR | read-write | 0x00000000
0x400E0710 | Receive Next Pointer Register | UART0_RNPR | read-write | 0x00000000
0x400E0714 | Receive Next Counter Register | UART0_RNCR | read-write | 0x00000000
0x400E0718 | Transmit Next Pointer Register | UART0_TNPR | read-write | 0x00000000
0x400E071C | Transmit Next Counter Register | UART0_TNCR | read-write | 0x00000000
0x400E0720 | Transfer Control Register | UART0_PTCR | write-only | 0x00000000
0x400E0724 | Transfer Status Register | UART0_PTSR | read-only | 0x00000000

### Register Fields

#### UART0 Control Register

Name: UART0_CR

Access: write-only

Address: 0x400E0600

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | RSTSTA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXDIS | TXEN | RXDIS | RXEN | RSTTX | RSTRX | - | -

- RSTRX: Reset Receiver

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | The receiver logic is reset and disabled. If a character is being received, the reception is aborted.

- RSTTX: Reset Transmitter

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.

- RXEN: Receiver Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | The receiver is enabled if RXDIS is 0.

- RXDIS: Receiver Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped.

- TXEN: Transmitter Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | The transmitter is enabled if TXDIS is 0.

- TXDIS: Transmitter Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | The transmitter is disabled. If a character is being processed and a character has been written in the UART_THR and RSTTX is not set, both characters are completed before the transmitter is stopped.

- RSTSTA: Reset Status Bits

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Resets the status bits PARE, FRAME and OVRE in the UART_SR.

#### UART0 Mode Register

Name: UART0_MR

Access: read-write

Address: 0x400E0604

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CHMODE | - | - | PAR | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | -

- PAR: Parity Type

  Value | Name | Description
  --- | --- | ---
  0x0 | EVEN | Even parity
  0x1 | ODD | Odd parity
  0x2 | SPACE | Space: parity forced to 0
  0x3 | MARK | Mark: parity forced to 1
  0x4 | NO | No parity

- CHMODE: Channel Mode

  Value | Name | Description
  --- | --- | ---
  0x0 | NORMAL | Normal Mode
  0x1 | AUTOMATIC | Automatic Echo
  0x2 | LOCAL_LOOPBACK | Local Loopback
  0x3 | REMOTE_LOOPBACK | Remote Loopback

#### UART0 Interrupt Enable Register

Name: UART0_IER

Access: write-only

Address: 0x400E0608

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | RXBUFF | TXBUFE | - | TXEMPTY | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PARE | FRAME | OVRE | ENDTX | ENDRX | - | TXRDY | RXRDY

- RXRDY: Enable RXRDY Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- TXRDY: Enable TXRDY Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- ENDRX: Enable End of Receive Transfer Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- ENDTX: Enable End of Transmit Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- OVRE: Enable Overrun Error Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- FRAME: Enable Framing Error Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- PARE: Enable Parity Error Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- TXEMPTY: Enable TXEMPTY Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- TXBUFE: Enable Buffer Empty Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- RXBUFF: Enable Buffer Full Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

#### UART0 Interrupt Disable Register

Name: UART0_IDR

Access: write-only

Address: 0x400E060C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | RXBUFF | TXBUFE | - | TXEMPTY | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PARE | FRAME | OVRE | ENDTX | ENDRX | - | TXRDY | RXRDY

- RXRDY: Disable RXRDY Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- TXRDY: Disable TXRDY Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- ENDRX: Disable End of Receive Transfer Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- ENDTX: Disable End of Transmit Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- OVRE: Disable Overrun Error Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- FRAME: Disable Framing Error Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- PARE: Disable Parity Error Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- TXEMPTY: Disable TXEMPTY Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- TXBUFE: Disable Buffer Empty Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- RXBUFF: Disable Buffer Full Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

#### UART0 Interrupt Mask Register

Name: UART0_IMR

Access: read-only

Address: 0x400E0610

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | RXBUFF | TXBUFE | - | TXEMPTY | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PARE | FRAME | OVRE | ENDTX | ENDRX | - | TXRDY | RXRDY

- RXRDY: Mask RXRDY Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- TXRDY: Disable TXRDY Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- ENDRX: Mask End of Receive Transfer Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- ENDTX: Mask End of Transmit Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- OVRE: Mask Overrun Error Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- FRAME: Mask Framing Error Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- PARE: Mask Parity Error Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- TXEMPTY: Mask TXEMPTY Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- TXBUFE: Mask TXBUFE Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

- RXBUFF: Mask RXBUFF Interrupt

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is disabled.
  1 | - | The corresponding interrupt is enabled.

#### UART0 Status Register

Name: UART0_SR

Access: read-only

Address: 0x400E0614

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | RXBUFF | TXBUFE | - | TXEMPTY | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PARE | FRAME | OVRE | ENDTX | ENDRX | - | TXRDY | RXRDY

- RXRDY: Receiver Ready

  Value | Name | Description
  --- | --- | ---
  0 | - | No character has been received since the last read of the UART_RHR or the receiver is disabled.
  1 | - | At least one complete character has been received, transferred to UART_RHR and not yet read.

- TXRDY: Transmitter Ready

  Value | Name | Description
  --- | --- | ---
  0 | - | A character has been written to UART_THR and not yet transferred to the Shift Register, or the transmitter is disabled.
  1 | - | There is no character written to UART_THR not yet transferred to the Shift Register.

- ENDRX: End of Receiver Transfer

  Value | Name | Description
  --- | --- | ---
  0 | - | The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive.
  1 | - | The End of Transfer signal from the receiver Peripheral Data Controller channel is active.

- ENDTX: End of Transmitter Transfer

  Value | Name | Description
  --- | --- | ---
  0 | - | The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive.
  1 | - | The End of Transfer signal from the transmitter Peripheral Data Controller channel is active.

- OVRE: Overrun Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No overrun error has occurred since the last RSTSTA.
  1 | - | At least one overrun error has occurred since the last RSTSTA.

- FRAME: Framing Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No framing error has occurred since the last RSTSTA.
  1 | - | At least one framing error has occurred since the last RSTSTA.

- PARE: Parity Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No parity error has occurred since the last RSTSTA.
  1 | - | At least one parity error has occurred since the last RSTSTA.

- TXEMPTY: Transmitter Empty

  Value | Name | Description
  --- | --- | ---
  0 | - | There are characters in UART_THR, or characters being processed by the transmitter, or the transmitter is disabled.
  1 | - | There are no characters in UART_THR and there are no characters being processed by the transmitter.

- TXBUFE: Transmission Buffer Empty

  Value | Name | Description
  --- | --- | ---
  0 | - | The buffer empty signal from the transmitter PDC channel is inactive.
  1 | - | The buffer empty signal from the transmitter PDC channel is active.

- RXBUFF: Receive Buffer Full

  Value | Name | Description
  --- | --- | ---
  0 | - | The buffer full signal from the receiver PDC channel is inactive.
  1 | - | The buffer full signal from the receiver PDC channel is active.

#### UART0 Receive Holding Register

Name: UART0_RHR

Access: read-only

Address: 0x400E0618

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXCHR

- RXCHR: Received Character

-

#### UART0 Transmit Holding Register

Name: UART0_THR

Access: write-only

Address: 0x400E061C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXCHR

- TXCHR: Character to be Transmitted

-

#### UART0 Baud Rate Generator Register

Name: UART0_BRGR

Access: read-write

Address: 0x400E0620

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CD

- CD: Clock Divisor

-

#### UART0 Receive Pointer Register

Name: UART0_RPR

Access: read-write

Address: 0x400E0700

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RXPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RXPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXPTR

- RXPTR: Receive Pointer Register

-

#### UART0 Receive Counter Register

Name: UART0_RCR

Access: read-write

Address: 0x400E0704

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXCTR

- RXCTR: Receive Counter Register

-

#### UART0 Transmit Pointer Register

Name: UART0_TPR

Access: read-write

Address: 0x400E0708

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TXPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TXPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXPTR

- TXPTR: Transmit Counter Register

-

#### UART0 Transmit Counter Register

Name: UART0_TCR

Access: read-write

Address: 0x400E070C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXCTR

- TXCTR: Transmit Counter Register

-

#### UART0 Receive Next Pointer Register

Name: UART0_RNPR

Access: read-write

Address: 0x400E0710

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RXNPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RXNPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXNPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXNPTR

- RXNPTR: Receive Next Pointer

-

#### UART0 Receive Next Counter Register

Name: UART0_RNCR

Access: read-write

Address: 0x400E0714

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXNCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXNCTR

- RXNCTR: Receive Next Counter

-

#### UART0 Transmit Next Pointer Register

Name: UART0_TNPR

Access: read-write

Address: 0x400E0718

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TXNPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TXNPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXNPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXNPTR

- TXNPTR: Transmit Next Pointer

-

#### UART0 Transmit Next Counter Register

Name: UART0_TNCR

Access: read-write

Address: 0x400E071C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXNCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXNCTR

- TXNCTR: Transmit Counter Next

-

#### UART0 Transfer Control Register

Name: UART0_PTCR

Access: write-only

Address: 0x400E0720

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | TXTDIS | TXTEN
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | RXTDIS | RXTEN

- RXTEN: Receiver Transfer Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables PDC receiver channel requests if RXTDIS is not set.

- RXTDIS: Receiver Transfer Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the PDC receiver channel requests.

- TXTEN: Transmitter Transfer Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the PDC transmitter channel requests.

- TXTDIS: Transmitter Transfer Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the PDC transmitter channel requests.

#### UART0 Transfer Status Register

Name: UART0_PTSR

Access: read-only

Address: 0x400E0724

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | TXTEN
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RXTEN

- RXTEN: Receiver Transfer Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | PDC Receiver channel requests are disabled.
  1 | - | PDC Receiver channel requests are enabled.

- TXTEN: Transmitter Transfer Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | PDC Transmitter channel requests are disabled.
  1 | - | PDC Transmitter channel requests are enabled.