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Large circuit models: opportunities and challenges

  • Position Paper
  • Open access
  • Published: 25 September 2024
  • Volume 67, article number 200402, (2024)
  • Cite this article

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Science China Information Sciences Aims and scope Submit manuscript
Large circuit models: opportunities and challenges
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  • Lei Chen5,
  • Yiqi Chen7,
  • Zhufei Chu6,
  • Wenji Fang3,
  • Tsung-Yi Ho1,
  • Ru Huang7,11,
  • Yu Huang4,
  • Sadaf Khan1,
  • Min Li5,
  • Xingquan Li9,
  • Yu Li1,
  • Yun Liang7,
  • Jinwei Liu1,
  • Yi Liu1,
  • Yibo Lin7,
  • Guojie Luo8,
  • Hongyang Pan2,
  • Zhengyuan Shi1,
  • Guangyu Sun7,
  • Dimitrios Tsaras5,
  • Runsheng Wang7,
  • Ziyi Wang1,
  • Xinming Wei8,
  • Zhiyao Xie3,
  • Qiang Xu1,
  • Chenhao Xue7,
  • Junchi Yan10,
  • Jun Yang11,
  • Bei Yu1,
  • Mingxuan Yuan5,
  • Evangeline F. Y. Young1,
  • Xuan Zeng2,
  • Haoyi Zhang7,
  • Zuodong Zhang7,
  • Yuxiang Zhao7,
  • Hui-Ling Zhen5,
  • Ziyang Zheng1,
  • Binwu Zhu1,
  • Keren Zhu1 &
  • …
  • Sunan Zou8 

  • 2956 Accesses

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An Erratum to this article was published on 21 October 2024

This article has been updated

Abstract

Within the electronic design automation (EDA) domain, artificial intelligence (AI)-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies. These solutions often repurpose deep learning models from other domains, such as vision, text, and graph analytics, applying them to circuit design without tailoring to the unique complexities of electronic circuits. Such an “AI4EDA” approach falls short of achieving a holistic design synthesis and understanding, overlooking the intricate interplay of electrical, logical, and physical facets of circuit data. This study argues for a paradigm shift from AI4EDA towards AI-rooted EDA from the ground up, integrating AI at the core of the design process. Pivotal to this vision is the development of a multimodal circuit representation learning technique, poised to provide a comprehensive understanding by harmonizing and extracting insights from varied data sources, such as functional specifications, register-transfer level (RTL) designs, circuit netlists, and physical layouts. We champion the creation of large circuit models (LCMs) that are inherently multimodal, crafted to decode and express the rich semantics and structures of circuit data, thus fostering more resilient, efficient, and inventive design methodologies. Embracing this AI-rooted philosophy, we foresee a trajectory that transcends the current innovation plateau in EDA, igniting a profound “shift-left” in electronic design methodology. The envisioned advancements herald not just an evolution of existing EDA tools but a revolution, giving rise to novel instruments of design-tools that promise to radically enhance design productivity and inaugurate a new epoch where the optimization of circuit performance, power, and area (PPA) is achieved not incrementally, but through leaps that redefine the benchmarks of electronic systems’ capabilities.

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Change history

  • 24 October 2024

    An Erratum to this paper has been published: https://doi.org/10.1007/s11432-024-4173-3

  • 21 October 2024

    An Erratum to this paper has been published: https://doi.org/10.1007/s11432-024-4173-3

References

  1. Bommasani R, Hudson D A, Adeli E, et al. On the opportunities and risks of foundation models. 2021. ArXiv:2108.07258

    Google Scholar 

  2. Devlin J, Chang M W, Lee K, et al. BERT: pre-training of deep bidirectional transformers for language understanding. In: Proceedings of Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies, 2019. 4171–4186

    Google Scholar 

  3. Liu Y, Ott M, Goyal N, et al. RoBERTa: a robustly optimized BERT pretraining approach. 2019. ArXiv:1907.11692

    Google Scholar 

  4. Raffel C, Shazeer N, Roberts A, et al. Exploring the limits of transfer learning with a unified text-to-text transformer. J Mach Learn Res, 2020, 21: 5485–5551

    MathSciNet  Google Scholar 

  5. Brown T, Mann B, Ryder N, et al. Language models are few-shot learners. In: Proceedings of Advances in Neural Information Processing Systems (NeurIPS), 2020. 33: 1877–1901

    Google Scholar 

  6. Chen T, Kornblith S, Norouzi M, et al. A simple framework for contrastive learning of visual representations. In: Proceedings of International Conference on Machine Learning (ICML), 2020. 1597–1607

    Google Scholar 

  7. He K, Fan H, Wu Y, et al. Momentum contrast for unsupervised visual representation learning. In: Proceedings of IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2020. 9729–9738

    Google Scholar 

  8. He K, Chen X, Xie S, et al. Masked autoencoders are scalable vision learners. In: Proceedings of IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2022. 16000–16009

    Google Scholar 

  9. Radford A, Kim J W, Hallacy C, et al. Learning transferable visual models from natural language supervision. In: Proceedings of International Conference on Machine Learning (ICML), 2021. 8748–8763

    Google Scholar 

  10. Ramesh A, Pavlov M, Goh G, et al. Zero-shot text-to-image generation. In: Proceedings of International Conference on Machine Learning (ICML), 2021. 8821–8831

    Google Scholar 

  11. Rombach R, Blattmann A, Lorenz D, et al. High-resolution image synthesis with latent diffusion models. In: Proceedings of IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2022. 10684–10695

    Google Scholar 

  12. Kirillov A, Mintun E, Ravi N, et al. Segment anything. 2023. ArXiv:2304.02643

    Book  Google Scholar 

  13. Yang Z, Li L, Lin K, et al. The dawn of LMMs: preliminary explorations with GPT-4V(ision). 2023. ArXiv:2309.17421

    Google Scholar 

  14. Team G, Anil R, Borgeaud S, et al. Gemini: a family of highly capable multimodal models. 2023. ArXiv:2312.11805

    Google Scholar 

  15. Rapp M, Amrouch H, Lin Y, et al. MLCAD: a survey of research in machine learning for CAD keynote paper. IEEE Trans Comput-Aided Des Integr Circ Syst, 2022, 41: 3162–3181

    Article  Google Scholar 

  16. Li M, Khan S, Shi Z, et al. DeepGate: learning neural representations of logic gates. In: Proceedings of ACM/IEEE Design Automation Conference, 2022. 667–672

    Chapter  Google Scholar 

  17. Shi Z, Pan H, Khan S, et al. DeepGate2: functionality-aware circuit representation learning. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023. 1–9

    Google Scholar 

  18. Xu Y, Yu Z, Tang D, et al. Towards developing high performance RISC-V processors using agile methodology. In: Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2022. 1178–1199

    Google Scholar 

  19. Asanovic K, Avizienis R, Bachrach J, et al. The Rocket Chip Generator. Technical Report UCB/EECS-2016-17, EECS Department, University of California, Berkeley, 2016

    Google Scholar 

  20. Vaswani A, Shazeer N, Parmar N, et al. Attention is all you need. In: Proceedings of Advances in Neural Information Processing Systems (NeurIPS), 2017

    Google Scholar 

  21. Zhou J, Cui G, Hu S, et al. Graph neural networks: a review of methods and applications. AI Open, 2020, 1: 57–81

    Article  Google Scholar 

  22. Baltrusaitis T, Ahuja C, Morency L P. Multimodal machine learning: a survey and taxonomy. IEEE Trans Pattern Anal Mach Intell, 2019, 41: 423–443

    Article  Google Scholar 

  23. Austin J, Odena A, Nye M, et al. Program synthesis with large language models. 2021. ArXiv:2108.07732

    Google Scholar 

  24. Lin C C, Chen K C, Chang S C, et al. Logic synthesis for engineering change. In: Proceedings of ACM/IEEE Design Automation Conference, 1995. 647–652

    Google Scholar 

  25. Micheli G. Chip challenge. IEEE Solid-State Circ Mag, 2010, 2: 22–26

    Article  Google Scholar 

  26. Bachrach J, Vo H, Richards B, et al. Chisel: constructing hardware in a Scala embedded language. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2012. 1216–1225

    Google Scholar 

  27. Johnson S C. Lint, a C Program Checker. Murray Hill: Bell Laboratories, 1977

    Google Scholar 

  28. Marquez C I C, Strum M, Chau W J. Formal equivalence checking between high-level and RTL hardware designs. In: Proceedings of the 14th Latin American Test Workshop-LATW, 2013. 1–6

    Google Scholar 

  29. Mukherjee R, Purandare M, Polig R, et al. Formal techniques for effective co-verification of hardware/software co-designs. In: Proceedings of the 54th Annual Design Automation Conference, 2017. 1–6

    Google Scholar 

  30. Synopsys. VC formal datapath validation. 2024. https://www.synopsys.com/verification/static-and-formal-verification/vc-formal/vc-formal-datapath-validation.html

    Google Scholar 

  31. Koelbl A, Jacoby R, Jain H, et al. Solver technology for system-level to RTL equivalence checking. In: Proceedings of Design, Automation & Test in Europe Conference & Exhibition, 2009. 196–201

    Google Scholar 

  32. Huang B Y, Zhang H, Subramanyan P, et al. Instruction-level abstraction (ILA) a uniform specification for system-on-chip (SoC) verification. ACM Trans Des Autom Electron Syst, 2018, 24: 1–24

    Article  Google Scholar 

  33. Mishchenko A, Chatterjee S, Brayton R, et al. Improvements to combinational equivalence checking. In: Proceedings of the IEEE/ACM International Conference on Computer-aided Design, 2006. 836–843

    Google Scholar 

  34. Baumgartner J, Mony H, Paruthi V, et al. Scalable sequential equivalence checking across arbitrary design transformations. In: Proceedings of International Conference on Computer Design, 2006. 259–266

    Google Scholar 

  35. Chen Z, Zhang X, Qian Y, et al. Integrating exact simulation into sweeping for datapath combinational equivalence checking. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023. 1–9

    Google Scholar 

  36. Dai Y Y, Khoo K Y, Brayton R K. Sequential equivalence checking of clock-gated circuits. In: Proceedings of the 52nd Annual Design Automation Conference, 2015. 1–6

    Google Scholar 

  37. Alpert C J, Mehta D P, Sapatnekar S S. Handbook of Algorithms for Physical Design Automation. Boca Raton: CRC Press, 2008

    Book  Google Scholar 

  38. Wong D, Leong H W, Liu H. Simulated Annealing for VLSI Design. Berlin: Springer Science & Business Media, 2012

    Google Scholar 

  39. Chang Y C, Chang Y W, Wu G M, et al. B*-trees: a new representation for non-slicing floorplans. In: Proceedings of the 37th Annual Design Automation Conference, 2000. 458–463

    Chapter  Google Scholar 

  40. Smith L D, Anderson R E, Forehand D W, et al. Power distribution system design methodology and capacitor selection for modern CMOS technology. IEEE Trans Adv Packag, 1999, 22: 284–291

    Article  Google Scholar 

  41. Zhu Q K. Power Distribution Network Design for VLSI. Hoboken: John Wiley & Sons, 2004

    Book  Google Scholar 

  42. Sehen C. An improved simulated annealing algorithm for row-based placement. In: Proceedings of IEEE International Conference on Computer-Aided Design, 1987. 478–481

    Google Scholar 

  43. Kleinhans J M, Sigl G, Johannes F M, et al. GORDIAN: VLSI placement by quadratic programming and slicing optimization. IEEE Trans Comput-Aided Des Integr Circ Syst, 1991, 10: 356–365

    Article  Google Scholar 

  44. Viswanathan N, Chu C C N. FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. In: Proceedings of the International Symposium on Physical Design, 2004. 26–33

    Google Scholar 

  45. Chen T C, Jiang Z W, Hsu T C, et al. NTUplace3: an analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. IEEE Trans Comput-Aided Des Integr Circ Syst, 2008, 27: 1228–1240

    Article  Google Scholar 

  46. Qiu Y, Xing Y, Zheng X, et al. Progress of placement optimization for accelerating VLSI physical design. Electronics, 2023, 12: 337

    Article  Google Scholar 

  47. Chao T H, Hsu Y C, Ho J M, et al. Zero skew clock routing with minimum wirelength. IEEE Trans Circ Syst II, 1992, 39: 799–814

    Google Scholar 

  48. Deng C, Cai Y, Zhou Q, et al. An efficient buffer sizing algorithm for clock trees considering process variations. In: Proceedings of the 6th Asia Symposium on Quality Electronic Design (ASQED), 2015. 108–113

    Google Scholar 

  49. Liu J, Pui C W, Wang F, et al. CUGR: detailed-routability-driven 3D global routing with probabilistic resource model. In: Proceedings of the 57th ACM/IEEE Design Automation Conference (DAC), 2020. 1–6

    Google Scholar 

  50. Liu W H, Kao W C, Li Y L, et al. NCTU-GR 2.0: multithreaded collision-aware global routing with bounded-length maze routing. IEEE Trans Comput-Aided Des Integr Circ Syst, 2013, 32: 709–722

    Article  Google Scholar 

  51. Betz V, Rose J. VPR: a new packing, placement and routing tool for FPGA research. In: Proceedings of International Workshop on Field Programmable Logic and Applications, 1997. 213–222

    Chapter  Google Scholar 

  52. Hu J, Sapatnekar S S. A survey on multi-net global routing for integrated circuits. Integration, 2001, 31: 1–49

    Article  Google Scholar 

  53. Stojilović M. Parallel FPGA routing: survey and challenges. In: Proceedings of the 27th International Conference on Field Programmable Logic and Applications (FPL), 2017. 1–8

    Google Scholar 

  54. Li X, Huang Z, Tao S, et al. iEDA: an open-source infracstructure of EDA. In: Proceedings of Asia and South Pacific Design Automation Conference (ASPDAC), 2024

    Google Scholar 

  55. Li Y L, Lin S T, Nishizawa S, et al. NCTUcell: a DDA-aware cell library generator for FinFET structure with implicitly adjustable grid map. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2019. 1–6

    Google Scholar 

  56. Cheng C K, Ho C T, Lee D, et al. A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020. 1–8

    Google Scholar 

  57. Park D, Lee D, Kang I, et al. SP&R: simultaneous placement and routing framework for standard cell synthesis in sub-7nm. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2020. 345–350

    Google Scholar 

  58. Choi S, Jung J, Kahng A B, et al. PROBE3.0: a systematic framework for design-technology pathfinding with improved design enablement. IEEE Trans Comput-Aided Des Integr Circ Syst, 2024, 43: 1218–1231

    Article  Google Scholar 

  59. Beaumont-Smith A, Lim C C. Parallel prefix adder design. In: Proceedings of the 15th IEEE Symposium on Computer Arithmetic, 2001. 218–225

    Google Scholar 

  60. Rakesh S, Grace K S V. A comprehensive review on the VLSI design performance of different Parallel Prefix Adders. Mater Today-Proc, 2019, 11: 1001–1009

    Article  Google Scholar 

  61. Liu J, Zhou S, Zhu H, et al. An algorithmic approach for generic parallel adders. In: Proceedings of International Conference on Computer Aided Design, 2003. 734–740

    Google Scholar 

  62. Matsunaga T, Matsunaga Y. Area minimization algorithm for parallel prefix adders under bitwise delay constraints. In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI, 2007. 435–440

    Chapter  Google Scholar 

  63. Roy S, Choudhury M, Puri R, et al. Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. In: Proceedings of the 50th Annual Design Automation Conference, 2013. 1–8

    Google Scholar 

  64. Wallace C S. A suggestion for a fast multiplier. IEEE Trans Electron Comput, 1964, EC-13: 14–17

    Article  Google Scholar 

  65. Dadda L. Some Schemes for Parallel Multipliers. Palo Alto: IEEE Computer Society Press, 1990

    Google Scholar 

  66. Xiao W, Qian W, Liu W. GOMIL: global optimization of multiplier by integer linear programming. In: Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021. 374–379

    Google Scholar 

  67. Synopsys. Designware ip. http://www.synopsys.com/designware, 2015

    Google Scholar 

  68. Corporation S P E. SPEC CPU 2017 benchmark. https://www.spec.org/cpu2017/

  69. Haseeb M, Saeed F. High performance computing framework for tera-scale database search of mass spectrometry data. Nat Comput Sci, 2021, 1: 550–561

    Article  Google Scholar 

  70. Buchmann J. Introduction to Cryptography. New York: Springer, 2004

    Book  Google Scholar 

  71. Mulgrew B, Grant P, Thompson J. Digital Signal Processing: Concepts and Applications. London: Red Globe Press, 2002

    Google Scholar 

  72. Parashar A, Raina P, Shao Y S, et al. Timeloop: a systematic approach to DNN accelerator evaluation. In: Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2019. 304–315

    Google Scholar 

  73. Bai C, Sun Q, Zhai J, et al. BOOM-Explorer: RISC-V BOOM microarchitecture design space exploration framework. In: Proceedings of IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021

    Google Scholar 

  74. Chen S, Zheng S, Bai C, et al. SoC-Tuner: an importance-guided exploration framework for DNN-targeting soc design. In: Proceedings of the 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 2024. 207–212

    Google Scholar 

  75. Venieris S I, Bouganis C S. fpgaConvNet: a framework for mapping convolutional neural networks on FPGAs. In: Proceedings of IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2016. 40–47

    Google Scholar 

  76. Wang J, Cong J. Search for optimal systolic arrays: a comprehensive automated exploration framework and lessons learned. 2021. ArXiv:2111.14252

    Google Scholar 

  77. Zhang D, Huda S, Songhori E, et al. A full-stack search technique for domain optimized deep learning accelerators. In: Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2022. 27–42

    Chapter  Google Scholar 

  78. Bai C, Huang J, Wei X, et al. ArchExplorer: microarchitecture exploration via bottleneck analysis. In: Proceedings of IEEE/ACM International Symposium on Microarchitecture (MICRO), 2023. 268–282

    Google Scholar 

  79. Dave S, Nowatzki T, Shrivastava A. Explainable-DSE: an agile and explainable exploration of efficient HW/SW codesigns of deep learning accelerators using bottleneck analysis. In: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023. 87–107

    Google Scholar 

  80. Budak A F, Pan D Z, Chen H, et al. CAD for Analog/Mixed-Signal Integrated Circuits. Piscataway: Wiley Press, 2023. 43–60

    Google Scholar 

  81. Budak A F, Zhang S, Liu M, et al. Machine Learning for Analog Circuit Sizing. Cham: Springer International Publishing, 2022. 307–335

    Google Scholar 

  82. Chen H, Liu M, Tang X, et al. Challenges and opportunities toward fully automated analog layout design. J Semicond, 2020, 41: 111407

    Article  Google Scholar 

  83. Zhao Z, Zhang L. An automated topology synthesis framework for analog integrated circuits. IEEE Trans Comput-Aided Des Integr Circ Syst, 2020, 39: 4325–4337

    Article  Google Scholar 

  84. Lyu W, Xue P, Yang F, et al. An efficient Bayesian optimization approach for automated optimization of analog circuits. IEEE Trans Circ Syst I, 2018, 65: 1954–1967

    Google Scholar 

  85. Zhu K, Chen H, Liu M, et al. Effective analog/mixed-signal circuit placement considering system signal flow. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020

    Google Scholar 

  86. Wu N, Xie Y, Hao C. AI-assisted synthesis in next generation EDA: promises, challenges, and prospects. In: Proceedings of IEEE 40th International Conference on Computer Design (ICCD), 2022. 207–214

    Google Scholar 

  87. Goswami P, Bhatia D. Application of machine learning in FPGA EDA tool development. IEEE Access, 2023, 11: 109564

    Article  Google Scholar 

  88. Koblah D, Acharya R, Capecci D, et al. A survey and perspective on artificial intelligence for security-aware electronic design automation. ACM Trans Des Autom Electron Syst, 2023, 28: 1–57

    Article  Google Scholar 

  89. Huang G, Hu J, He Y, et al. Machine learning for electronic design automation: a survey. ACM Trans Des Autom Electron Syst, 2021, 26: 1–46

    Article  Google Scholar 

  90. Lopera D S, Servadei L, Kiprit G N, et al. A survey of graph neural networks for electronic design automation. In: Proceedings of ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD), 2021. 1–6

    Google Scholar 

  91. Lin Y, Ziv A, Ren H. Introduction to the special issue on machine learning for CAD/EDA. ACM Trans Des Autom Electron Syst, 2023, 28: 1–2

    Article  Google Scholar 

  92. Ren H, Hu J. Machine Learning Applications in Electronic Design Automation. Berlin: Springer, 2022

    Book  Google Scholar 

  93. Joseph P, Vaswani K, Thazhuthaveetil M J. Construction and use of linear regression models for processor performance analysis. In: Proceedings of IEEE International Symposium on High Performance Computer Architecture (HPCA), 2006

    Google Scholar 

  94. Mendis C, Renda A, Amarasinghe S, et al. Ithemal: accurate, portable and fast basic block throughput estimation using deep neural networks. In: Proceedings of International Conference on Machine Learning (ICML), 2019

    Google Scholar 

  95. Zhai J, Bai C, Zhu B, et al. McPAT-Calib: a microarchitecture power modeling framework for modern CPUs. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2021. 1–9

    Google Scholar 

  96. Zhang Q, Li S, Zhou G, et al. PANDA: architecture-level power evaluation by unifying analytical and machine learning solutions. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2023. 1–9

    Google Scholar 

  97. Ardalani N, Lestourgeon C, Sankaralingam K, et al. Cross-architecture performance prediction (XAPP) using CPU code to predict GPU performance. In: Proceedings of IEEE/ACM International Symposium on Microarchitecture (MICRO), 2015

    Google Scholar 

  98. Wu G, Greathouse J L, Lyashevsky A, et al. GPGPU performance and power estimation using machine learning. In: Proceedings of IEEE International Symposium on High Performance Computer Architecture (HPCA), 2015

    Google Scholar 

  99. Qian Z, Juan D C, Bogdan P, et al. SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2013. 354–357

    Google Scholar 

  100. Shi Z, Huang X, Jain A, et al. Applying deep learning to the cache replacement problem. In: Proceedings of IEEE/ACM International Symposium on Microarchitecture (MICRO), 2019. 413–425

    Google Scholar 

  101. Bera R, Kanellopoulos K, Nori A, et al. Pythia: a customizable hardware prefetching framework using online reinforcement learning. In: Proceedings of IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021

    Google Scholar 

  102. Lu S, Tessier R, Burleson W. Reinforcement learning for thermal-aware many-core task allocation. In: Proceedings of Great Lakes Symposium on VLSI, 2015

    Google Scholar 

  103. AbouGhazaleh N, Ferreira A, Rusu C, et al. Integrated CPU and L2 cache voltage scaling using machine learning. In: Proceedings of ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2007

    Google Scholar 

  104. Dubach C, Jones T M, Bonilla E V, et al. A predictive model for dynamic microarchitectural adaptivity control. In: Proceedings of IEEE/ACM International Symposium on Microarchitecture (MICRO), 2010. 485–496

    Google Scholar 

  105. Kao S C, Jeong G, Krishna T. ConfuciuX: autonomous hardware resource assignment for DNN accelerators using reinforcement learning. In: Proceedings of IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020. 622–636

    Google Scholar 

  106. Dai S, Zhou Y, Zhang H, et al. Fast and accurate estimation of quality of results in high-level synthesis with machine learning. In: Proceedings of Symposium on Field-Programmable Custom Computing Machines (FCCM), 2018

    Google Scholar 

  107. Makrani H M, Farahmand F, Sayadi H, et al. Pyramid: machine learning framework to estimate the optimal timing and resource usage of a high-level synthesis design. In: Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), 2019

    Google Scholar 

  108. Ustun E, Deng C, Pal D, et al. Accurate operation delay prediction for FPGA HLS using graph neural networks. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020. 1–9

    Google Scholar 

  109. Zhao J, Liang T, Sinha S, et al. Machine learning based routing congestion prediction in FPGA high-level synthesis. In: Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019. 1130–1135

    Google Scholar 

  110. Lin Z, Yuan Z, Zhao J, et al. PowerGear: early-stage power estimation in FPGA HLS via heterogeneous edge-centric GNNs. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2022. 1341–1346

    Google Scholar 

  111. Liu H Y, Carloni L P. On learning-based methods for design-space exploration with high-level synthesis. In: Proceedings of Design Automation Conference (DAC), 2013

    Google Scholar 

  112. Meng P, Althoff A, Gautier Q, et al. Adaptive threshold non-Pareto elimination: re-thinking machine learning for system level design space exploration on FPGAs. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2016. 918–923

    Google Scholar 

  113. Kim R G, Doppa J R, Pande P P. Machine learning for design space exploration and optimization of manycore systems. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018. 1–6

    Google Scholar 

  114. Mahapatra A, Schafer B C. Machine-learning based simulated annealer method for high level synthesis design space exploration. In: Proceedings of Electronic System Level Synthesis Conference (ESLsyn), 2014. 1–6

    Google Scholar 

  115. Wang Z, Schafer B C. Machine leaming to set meta-heuristic specific parameters for high-level synthesis design space exploration. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2020. 1–6

    Google Scholar 

  116. Sun Q, Chen T, Liu S, et al. Correlated multi-objective multi-fidelity optimization for HLS directives design. ACM Trans Des Autom Electron Syst, 2022, 27: 1–27

    Article  Google Scholar 

  117. Yu Z, Bail C, Hu S, et al. IT-DSE: invariance risk minimized transfer microarchitecture design space exploration. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023. 1–9

    Google Scholar 

  118. Xiao Q, Zheng S, Wu B, et al. HASCO: towards agile hardware and software co-design for tensor computation. In: Proceedings of IEEE/ACM International Symposium on Computer Architecture (ISCA), 2021. 1055–1068

    Google Scholar 

  119. Xu C, Kjellqvist C, Wills L W. SNS’s not a synthesizer: a deep-learning-based synthesis predictor. In: Proceedings of International Symposium on Computer Architecture (ISCA), 2022

    Google Scholar 

  120. Sengupta P, Tyagi A, Chen Y, et al. How good is your Verilog RTL code? A quick answer from machine learning. In: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

    Google Scholar 

  121. Xu C, Sharma P, Wang T, et al. Fast, robust and transferable prediction for hardware logic synthesis. In: Proceedings of IEEE/ACM International Symposium on Microarchitecture, 2023. 167–179

    Chapter  Google Scholar 

  122. Fang W, Lu Y, Liu S, et al. MasterRTL: a pre-synthesis PPA estimation framework for any RTL design. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2023

    Google Scholar 

  123. Lopera D S, Ecker W. Applying GNNs to timing estimation at RTL. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2022

    Google Scholar 

  124. Wu N, Lee J, Xie Y, et al. LOSTIN: logic optimization via spatio-temporal information with hybrid graph models. In: Proceedings of International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2022

    Google Scholar 

  125. Zhou Y, Ren H, Zhang Y, et al. PRIMAL: power inference using machine learning. In: Proceedings of Design Automation Conference (DAC), 2019

    Google Scholar 

  126. Lee D, John L K, Gerstlauer A. Dynamic power and performance back-annotation for fast and accurate functional hardware simulation. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2015

    Google Scholar 

  127. Kumar A K A, Gerstlauer A. Learning-based CPU power modeling. In: Proceedings of ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2019

    Google Scholar 

  128. Xie Z, Li S, Ma M, et al. DEEP: developing extremely efficient runtime on-chip power meters. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2022

    Google Scholar 

  129. Zoni D, Cremona L, Fornaciari W. PowerProbe: run-time power modeling through automatic RTL instrumentation. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2018

    Google Scholar 

  130. Pagliari D J, Peluso V, Chen Y, et al. ALL-digital embedded meters for on-line power estimation. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2018

    Google Scholar 

  131. Xie Z, Xu X, Walker M, et al. APOLLO: an automated power modeling framework for runtime power introspection in high-volume commercial microprocessors. In: Proceedings of IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021

    Google Scholar 

  132. Kim D, Zhao J, Bachrach J, et al. Simmani: runtime power modeling for arbitrary RTL with automatic signal selection. In: Proceedings of IEEE/ACM International Symposium on Microarchitecture (MICRO), 2019

    Google Scholar 

  133. Yang J, Ma L, Zhao K, et al. Early stage real-time SoC power estimation using RTL instrumentation. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2015

    Google Scholar 

  134. Fine S, Ziv A. Coverage directed test generation for functional verification using Bayesian networks. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2003

    Google Scholar 

  135. Vasudevan S, Jiang W J, Bieber D, et al. Learning semantic representations to verify hardware designs. In: Proceedings of Advances in Neural Information Processing Systems (NeurIPS), 2021. 34: 23491–23504

    Google Scholar 

  136. Katz Y, Rimon M, Ziv A, et al. Learning microarchitectural behaviors to improve stimuli generation quality. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2011

    Google Scholar 

  137. Rai S, Neto W L, Miyasaka Y, et al. Logic synthesis meets machine learning: trading exactness for generalization. In: Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021. 1026–1031

    Google Scholar 

  138. Kahng A B, Wang Z. ML for design QoR prediction. In: Proceedings of Machine Learning Applications in Electronic Design Automation, 2022

    Google Scholar 

  139. Gogri S, Hu J, Tyagi A, et al. Machine learning-guided stimulus generation for functional verification. In: Proceedings of the Design and Verification Conference (DVCON-USA), 2020. 2–5

    Google Scholar 

  140. Xie Z, Pan J, Chang C C, et al. The dark side: security and reliability concerns in machine learning for EDA. IEEE Trans Comput-Aided Des Integr Circ Syst, 2022, 42: 1171–1184

    Article  Google Scholar 

  141. Neto W L, Austin M, Temple S, et al. LSOracle: a logic synthesis framework driven by artificial intelligence. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019. 1–6

    Google Scholar 

  142. Neto W L, Moreira M T, Li Y, et al. SLAP: a supervised learning approach for priority cuts technology mapping. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2021. 859–864

    Google Scholar 

  143. Neto W L, Moreira M T, Amaru L, et al. Read your circuit: leveraging word embedding to guide logic optimization. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2021. 530–535

    Google Scholar 

  144. Yu C, Xiao H, Micheli G. Developing synthesis flows without human knowledge. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2018

    Google Scholar 

  145. Yu C, Zhou W. Decision making in synthesis cross technologies using LSTMs and transfer learning. In: Proceedings of ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2020. 55–60

    Google Scholar 

  146. Pei Z, Liu F, He Z, et al. AlphaSyn: logic synthesis optimization with efficient Monte Carlo tree search. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023. 1–9

    Google Scholar 

  147. Yuan J, Wang P, Ye J, et al. EasySO: exploration-enhanced reinforcement learning for logic synthesis sequence optimization and a comprehensive RL environment. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023. 1–9

    Google Scholar 

  148. Xie Z, Liang R, Xu X, et al. Preplacement net length and timing estimation by customized graph neural network. IEEE Trans Comput-Aided Des Integr Circ Syst, 2022, 41: 4667–4680

    Article  Google Scholar 

  149. Zhong R, Ye J, Tang Z, et al. PreRoutGNN for timing prediction with order preserving partition: global circuit pre-training, local delay learning and attentional cell modeling. AAAI, 2024, 38: 17087–17095

    Article  Google Scholar 

  150. Zhang Y, Ren H, Khailany B. GRANNITE: graph neural network inference for transferable power estimation. In: Proceedings of Design Automation Conference (DAC), 2020

    Google Scholar 

  151. Rakesh M, Das P, Terkar A, et al. GRASPE: accurate post-synthesis power estimation from RTL using graph representation learning. In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2023. 1–5

    Google Scholar 

  152. Khan S, Shi Z, Li M, et al. DeepSeq: deep sequential circuit learning. 2023. ArXiv:2302.13608

    Google Scholar 

  153. Chowdhury S D, Yang K, Nuzzo P. ReIGNN: state register identification using graph neural networks for circuit reverse engineering. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2021. 1–9

    Google Scholar 

  154. Alrahis L, Sengupta A, Knechtel J, et al. GNN-RE: graph neural networks for reverse engineering of gate-level netlists. IEEE Trans Comput-Aided Des Integr Circ Syst, 2021, 41: 2435–2448

    Article  Google Scholar 

  155. He Z, Wang Z, Bail C, et al. Graph learning-based arithmetic block identification. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2021. 1–8

    Google Scholar 

  156. Wu N, Li Y, Hao C, et al. Gamora: graph learning based symbolic reasoning for large-scale Boolean networks. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2023

    Google Scholar 

  157. Shin Y. AI-EDA: toward a holistic approach to AI-powered EDA. In: Proceedings of ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD), 2023. 1–3

    Google Scholar 

  158. Amuru D, Zahra A, Vudumula H V, et al. AI/ML algorithms and applications in VLSI design and technology. Integration, 2023, 93: 102048

    Article  Google Scholar 

  159. Li W, Chen G, Yang H, et al. Learning point clouds in EDA. In: Proceedings of the International Symposium on Physical Design, 2021. 55–62

    Google Scholar 

  160. Chen T, Zhang G L, Yu B, et al. Machine learning in advanced IC design: a methodological survey. IEEE Des Test, 2023, 40: 17–33

    Article  Google Scholar 

  161. Ward S, Ding D, Pan D Z. PADE: a high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2012. 756–761

    Google Scholar 

  162. Lin Y, Dhar S, Li W, et al. DREAMPlace: deep learning toolkit-enabled GPU acceleration for modern VLSI placement. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2019. 1–6

    Google Scholar 

  163. Agnesina A, Rajvanshi P, Yang T, et al. AutoDMP: automated DREAMPlace-based macro placement. In: Proceedings of ACM International Symposium on Physical Design (ISPD), 2023

    Google Scholar 

  164. Xie Z, Huang Y H, Fang G Q, et al. RouteNet: routability prediction for mixed-size designs using convolutional neural network. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018

    Google Scholar 

  165. Huang Y H, Xie Z, Fang G Q, et al. Routability-driven macro placement with embedded CNN-based prediction model. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2019

    Google Scholar 

  166. Chang C C, Pan J, Zhang T, et al. Automatic routability predictor development using neural architecture search. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2021

    Google Scholar 

  167. Pan J, Chang C C, Xie Z, et al. Towards collaborative intelligence: routability estimation based on decentralized private data. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2022

    Google Scholar 

  168. Zheng S, Zou L, Xu P, et al. Lay-Net: grafting netlist knowledge on layout-based congestion prediction. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023. 1–9

    Google Scholar 

  169. Liu S, Sun Q, Liao P, et al. Global placement with deep learning-enabled explicit routability optimization. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), 2021. 1821–1824

    Google Scholar 

  170. Chen J, Kuang J, Zhao G, et al. PROS: a plug-in for routability optimization applied in the state-of-the-art commercial EDA tool using deep learning. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020

    Google Scholar 

  171. Zheng S, Zou L, Liu S, et al. Mitigating distribution shift for congestion optimization in global placement. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2023. 1–6

    Google Scholar 

  172. Barboza E C, Shukla N, Chen Y, et al. Machine learning-based pre-routing timing prediction with reduced pessimism. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2019

    Google Scholar 

  173. He X, Fu Z, Wang Y, et al. Accurate timing prediction at placement stage with look-ahead RC network. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2022. 1213–1218

    Chapter  Google Scholar 

  174. Cao P, He G, Yang T. TF-Predictor: transformer-based prerouting path delay prediction framework. IEEE Trans Comput-Aided Des Integr Circ Syst, 2023, 42: 2227–2237

    Article  Google Scholar 

  175. Guo Z, Liu M, Gu J, et al. A timing engine inspired graph neural network model for pre-routing slack prediction. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2022. 1207–1212

    Chapter  Google Scholar 

  176. Wang Z, Liu S, Pu Y, et al. Restructure-tolerant timing prediction via multimodal fusion. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2023. 1–6

    Google Scholar 

  177. Liang R, Xie Z, Jung J, et al. Routing-free crosstalk prediction. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020

    Google Scholar 

  178. Liu S, Wang Z, Liu F, et al. Concurrent sign-off timing optimization via deep Steiner points refinement. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2023. 1–6

    Google Scholar 

  179. Kahng A B, Mallappa U, Saul L. Using machine learning to predict path-based slack from graph-based timing analysis. In: Proceedings of IEEE International Conference on Computer Design (ICCD), 2018. 603–612

    Google Scholar 

  180. Ye Y, Chen T, Gao Y, et al. Graph-learning-driven path-based timing analysis results predictor from graph-based timing analysis. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2023. 547–552

    Google Scholar 

  181. Ho C T, Kahng A B. IncPIRD: fast learning-based prediction of incremental IR drop. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019

    Google Scholar 

  182. Pao C H, Su A Y, Lee Y M. XGBIR: an XGBoost-based IR drop predictor for power delivery network. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2020. 1307–1310

    Google Scholar 

  183. Fang Y C, Lin H Y, Sui M Y, et al. Machine-learning-based dynamic IR drop prediction for ECO. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018. 1–7

    Google Scholar 

  184. Alawieh M B, Lin Y, Zhang Z, et al. GAN-SRAF: subresolution assist feature generation using generative adversarial networks. IEEE Trans Comput-Aided Des Integr Circ Syst, 2020, 40: 373–385

    Article  Google Scholar 

  185. Yang H, Li S, Deng Z, et al. GAN-OPC: mask optimization with lithography-guided generative adversarial nets. IEEE Trans Comput-Aided Des Integr Circ Syst, 2020, 39: 2822–2834

    Article  Google Scholar 

  186. Chen G, Yu Z, Liu H, et al. DevelSet: deep neural level set for instant mask optimization. IEEE Trans Comput-Aided Des Integr Circ Syst, 2023, 42: 5020–5033

    Article  Google Scholar 

  187. Zhu B, Zheng S, Yu Z, et al. L2O-ILT: learning to optimize inverse lithography techniques. IEEE Trans Comput-Aided Des Integr Circ Syst, 2024, 43: 944–955

    Article  Google Scholar 

  188. Watanabe Y, Kimura T, Matsunawa T, et al. Accurate lithography simulation model based on convolutional neural networks. In: Proceedings of SPIE, 2017. 137–145

    Google Scholar 

  189. Ye W, Alawieh M B, Lin Y, et al. LithoGAN: end-to-end lithography modeling with generative adversarial networks. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2019

    Google Scholar 

  190. Lin Y, Li M, Watanabe Y, et al. Data efficient lithography modeling with transfer learning and active data selection. IEEE Trans Comput-Aided Des Integr Circ Syst, 2018, 38: 1900–1913

    Article  Google Scholar 

  191. Chen G, Pei Z, Yang H, et al. Physics-informed optical kernel regression using complex-valued neural fields. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2023. 1–6

    Google Scholar 

  192. Yang H, Luo L, Su J, et al. Imbalance aware lithography hotspot detection: a deep learning approach. J Micro Nanolith MEMS MOEMS, 2017, 16: 033504

    Article  Google Scholar 

  193. Chen J, Lin Y, Guo Y, et al. Lithography hotspot detection using a double inception module architecture. J Micro Nanolith MEMS MOEMS, 2019, 18: 013507

    Article  Google Scholar 

  194. Jiang Y, Yang F, Yu B, et al. Efficient layout hotspot detection via binarized residual neural network ensemble. IEEE Trans Comput-Aided Des Integr Circ Syst, 2020, 40: 1476–1488

    Article  Google Scholar 

  195. Ciccazzo A, Pillo G D, Latorre V. A SVM surrogate model-based method for parametric yield optimization. IEEE Trans Comput-Aided Des Integr Circ Syst, 2015, 35: 1224–1228

    Article  Google Scholar 

  196. Nakata K, Orihara R, Mizuoka Y, et al. A comprehensive big-data-based monitoring system for yield enhancement in semiconductor manufacturing. IEEE Trans Semicond Manufact, 2017, 30: 339–344

    Article  Google Scholar 

  197. Alawieh M B, Boning D, Pan D Z. Wafer map defect patterns classification using deep selective learning. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2020. 1–6

    Google Scholar 

  198. Kwon J, Ziegler M M, Carloni L P. A learning-based recommender system for autotuning design flows of industrial highperformance processors. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2019

    Google Scholar 

  199. Xie Z, Fang G Q, Huang Y H, et al. FIST: a feature-importance sampling and tree-based method for automatic design flow parameter tuning. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2020

    Google Scholar 

  200. Geng H, Chen T, Ma Y, et al. PTPT: physical design tool parameter tuning via multi-objective Bayesian optimization. IEEE Trans Comput-Aided Des Integr Circ Syst, 2022, 42: 178–189

    Article  Google Scholar 

  201. Cho M, Yuan K, Ban Y, et al. ELIAD: efficient lithography aware detailed routing algorithm with compact and macro post-OPC printability prediction. IEEE Trans Comput-Aided Des Integr Circ Syst, 2009, 28: 1006–1016

    Article  Google Scholar 

  202. Synopsys. Synopsys.ai unveiled as industry’s first full-stack, AI-driven EDA suite for chipmakers. 2023. https://news.synopsys.com/2023-03-29-Synopsys-ai-Unveiled-as-Industrys-First-Full-Stack,-AI-Driven-EDA-Suite-for-Chipmakers

    Google Scholar 

  203. Liu G, Zhang Z. PIMap: a flexible framework for improving LUT-based technology mapping via parallelized iterative optimization. ACM Trans Reconfig Technol Syst, 2018, 11: 1–23

    Google Scholar 

  204. Yu C. FlowTune: practical multi-armed bandits in Boolean optimization. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020. 1–9

    Google Scholar 

  205. Zhu K, Liu M, Chen H, et al. Exploring logic optimizations with reinforcement learning and graph convolutional network. In: Proceedings of ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2020. 145–150

    Google Scholar 

  206. Hosny A, Hashemi S, Shalan M, et al. DRiLLS: deep reinforcement learning for logic synthesis. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2020. 581–586

    Google Scholar 

  207. Peruvemba Y V, Rai S, Ahuja K, et al. RL-guided runtime-constrained heuristic exploration for logic synthesis. In: Proceedings of IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021. 1–9

    Google Scholar 

  208. Haaswijk W, Collins E, Seguin B, et al. Deep learning for logic optimization algorithms. In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2018. 1–4

    Google Scholar 

  209. Timoneda X, Cavigelli L. Late breaking results: reinforcement learning for scalable logic optimization with graph neural networks. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2021. 1378–1379

    Google Scholar 

  210. Mirhoseini A, Goldie A, Yazgan M, et al. A graph placement methodology for fast chip design. Nature, 2021, 594: 207–212

    Article  Google Scholar 

  211. Xu Q, Geng H, Chen S, et al. GoodFloorplan: graph convolutional network and reinforcement learning-based floorplanning. IEEE Trans Comput-Aided Des Integr Circ Syst, 2021, 41: 3492–3502

    Article  Google Scholar 

  212. Cheng R, Yan J. On joint learning for solving placement and routing in chip design. In: Proceedings of Advances in Neural Information Processing Systems, 2021. 34: 16508–16519

    Google Scholar 

  213. Cheng R, Lyu X, Li Y, et al. The policy-gradient placement and generative routing neural networks for chip design. In: Proceedings of Advances in Neural Information Processing Systems, 2022. 35: 26350–26362

    Google Scholar 

  214. Du X, Wang C, Zhong R, et al. HubRouter: learning global routing via hub generation and pin-hub connection. In: Proceedings of Advances in Neural Information Processing Systems, 2024

    Google Scholar 

  215. Agnesina A, Chang K, Lim S K. VLSI placement parameter optimization using deep reinforcement learning. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2020. 1–9

    Google Scholar 

  216. Lu Y C, Nath S, Khandelwal V, et al. RL-Sizer: VLSI gate sizing for timing optimization using deep reinforcement learning. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2021. 733–738

    Google Scholar 

  217. Lu Y C, Chan W T, Guo D, et al. RL-CCD: concurrent clock and data optimization using attention-based self-supervised reinforcement learning. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2023. 1–6

    Google Scholar 

  218. Liang X, Ouyang Y, Yang H, et al. RL-OPC: mask optimization with deep reinforcement learning. IEEE Trans Comput-Aided Des Integr Circ Syst, 2024, 43: 340–351

    Article  Google Scholar 

  219. Lu Y C, Lee J, Agnesina A, et al. GAN-CTS: a generative adversarial framework for clock tree prediction and optimization. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019

    Google Scholar 

  220. Lu Y, Liu S, Zhang Q, et al. RTLLM: an open-source benchmark for design RTL generation with large language model. 2023. ArXiv:2308.05345

    Google Scholar 

  221. Liu M, Pinckney N, Khailany B, et al. VerilogEval: evaluating large language models for Verilog code generation. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2023

    Google Scholar 

  222. Liang X. Hardware descriptions code completion based on a pre-training model. In: Proceedings of IEEE Conference on Telecommunications, Optics and Computer Science (TOCS), 2021. 228–232

    Google Scholar 

  223. Chang K, Wang Y, Ren H, et al. ChipGPT: how far are we from natural language hardware design. 2023. ArXiv:2305.14019

    Google Scholar 

  224. Thakur S, Blocklove J, Pearce H, et al. AutoChip: automating HDL generation using LLM feedback. 2023. ArXiv:2311.04887

    Google Scholar 

  225. Blocklove J, Garg S, Karri R, et al. Chip-Chat: challenges and opportunities in conversational hardware design. In: Proceedings of ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD), 2023

    Google Scholar 

  226. Liu M, Ene T D, Kirby R, et al. ChipNeMo: domain-adapted LLMs for chip design. 2023. ArXiv:2311.00176

    Google Scholar 

  227. Liu S, Fang W, Lu Y, et al. RTLCoder: outperforming GPT-3.5 in design RTL generation with our open-source dataset and lightweight solution. 2023. ArXiv:2312.08617

    Google Scholar 

  228. Pei Z, Zhen H L, Yuan M, et al. BetterV: controlled Verilog generation with discriminative guidance. 2024. ArXiv:2402.03375

    Google Scholar 

  229. Orenes-Vera M, Martonosi M, Wentzlaff D. Using LLMs to facilitate formal verification of RTL. 2023. ArXiv:2309.09437

    Google Scholar 

  230. Sun C, Hahn C, Trippel C. Towards improving verification productivity with circuit-aware translation of natural language to SystemVerilog assertions. In: Proceedings of the 1st International Workshop on Deep Learning-aided Verification (DAV), 2023

    Google Scholar 

  231. Fang W, Li M, Li M, et al. AssertLLM: generating and evaluating hardware verification assertions from design specifications via multi-LLMs. 2024. ArXiv:2402.00386

    Google Scholar 

  232. Zhang Y, Zhen H L, Pei Z, et al. SoLA: solver-layer adaption of LLM for better logic reasoning. 2024. ArXiv:2402.11903

    Google Scholar 

  233. Ahmad B, Thakur S, Tan B, et al. Fixing hardware security bugs with large language models. 2023. ArXiv:2302.01215

    Google Scholar 

  234. Nair M, Sadhukhan R, Mukhopadhyay D. Generating secure hardware using ChatGPT resistant to CWEs. Cryptology ePrint Archive, 2023. https://eprint.iacr.org/2023/212

    Google Scholar 

  235. Kande R, Pearce H, Tan B, et al. LLM-assisted generation of hardware assertions. 2023. ArXiv:2306.14027v1

    Google Scholar 

  236. He Z, Wu H, Zhang X, et al. ChatEDA: a large language model powered autonomous agent for EDA. 2023. ArXiv:2308.10204

    Google Scholar 

  237. Fu Y, Zhang Y, Yu Z, et al. GPT4AIGChip: towards next-generation AI accelerator design automation via large language models. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023. 1–9

    Google Scholar 

  238. Yan Z, Qin Y, Hu X S, et al. On the viability of using LLMs for SW/HW co-design: an example in designing CiM DNN accelerators. 2023. ArXiv:2306.06923

    Google Scholar 

  239. Liang Z, Cheng J, Yang R, et al. Unleashing the potential of LLMs for quantum computing: a study in quantum architecture design. 2023. ArXiv:2307.08191

    Google Scholar 

  240. Li M, Fang W, Zhang Q, et al. SpecLLM: exploring generation and review of VLSI design specification with large language model. 2024. ArXiv:2401.13266

    Google Scholar 

  241. Ren H, Fojtik M. Invited-NVCell: standard cell layout in advanced technology nodes with reinforcement learning. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2021. 1291–1294

    Google Scholar 

  242. Ren H, Fojtik M. Standard cell routing with reinforcement learning and genetic algorithm in advanced technology nodes. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2021. 684–689

    Google Scholar 

  243. Liang A C W, Wen C H P, Huang H M. A general and automatic cell layout generation framework with implicit learning on design rules. IEEE Trans VLSI Syst, 2022, 30: 1341–1354

    Article  Google Scholar 

  244. Roy S, Ma Y, Miao J, et al. A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders. In: Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2017. 1–6

    Google Scholar 

  245. Geng H, Ma Y, Xu Q, et al. High-speed adder design space exploration via graph neural processes. IEEE Trans Comput-Aided Des Integr Circ Syst, 2022, 41: 2657–2670

    Article  Google Scholar 

  246. Cheng J, Xiao Y, Shao Y, et al. Machine-learning-driven architectural selection of adders and multipliers in logic synthesis. ACM Trans Des Autom Electron Syst, 2023, 28: 1–16

    Google Scholar 

  247. Zuo D, Ouyang Y, Ma Y. RL-MUL: multiplier design optimization with deep reinforcement learning. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2023. 1–6

    Google Scholar 

  248. Zhu K, Chen H, Turner W J, et al. TAG: learning circuit spatial embedding from layouts. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2022

    Google Scholar 

  249. Lu J, Lei L, Yang F, et al. Topology optimization of operational amplifier in continuous space via graph embedding. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2022. 142–147

    Google Scholar 

  250. Fan S, Cao N, Zhang S, et al. From specification to topology: automatic power converter design via reinforcement learning. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2021

    Google Scholar 

  251. Zhao Z, Luo J, Liu J, et al. Signal-division-aware analog circuit topology synthesis aided by transfer learning. IEEE Trans Comput-Aided Des Integr Circ Syst, 2023, 42: 3481–3490

    Article  Google Scholar 

  252. Poddar S, Budak A, Zhao L, et al. A data-driven analog circuit synthesizer with automatic topology selection and sizing. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2024

    Google Scholar 

  253. Lu J, Li Y, Yang F, et al. High-level topology synthesis method for Δ-Σ modulators via bi-level Bayesian optimization. IEEE Trans Circ Syst II, 2023, 70: 4389–4393

    Google Scholar 

  254. Fayazi M, Taba M T, Afshari E, et al. AnGeL: fully-automated analog circuit generator using a neural network assisted semi-supervised learning approach. IEEE Trans Circuits Syst I, 2023, 70: 4516–4529

    Article  Google Scholar 

  255. Hakhamaneshi K, Nassar M, Phielipp M, et al. Pretraining graph neural networks for few-shot analog circuit modeling and design. IEEE Trans Comput-Aided Des Integr Circ Syst, 2023, 42: 2163–2173

    Article  Google Scholar 

  256. Budak A F, Gandara M, Shi W, et al. An efficient analog circuit sizing method based on machine learning assisted global optimization. IEEE Trans Comput-Aided Des Integr Circ Syst, 2022, 41: 1209–1221

    Article  Google Scholar 

  257. Wang H, Wang K, Yang J, et al. GCN-RL circuit designer: transferable transistor sizing with graph neural networks and reinforcement learning. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2020

    Google Scholar 

  258. Zhao A, Wang X, Lin Z, et al. cVTS: a constrained Voronoi tree search method for high dimensional analog circuit synthesis. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2023. 1–6

    Google Scholar 

  259. Burns S M, Chen H, Dhar T, et al. Machine Learning for Analog Layout. Cham: Springer International Publishing, 2022. 505–544

    Google Scholar 

  260. Kunal K, Poojary P, Dhar T, et al. A general approach for identifying hierarchical symmetry constraints for analog circuit layout. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020

    Google Scholar 

  261. Zhu K, Chen H, Liu M, et al. Automating analog constraint extraction: from heuristics to learning: (invited paper). In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2022. 108–113

    Google Scholar 

  262. Zhu K, Liu M, Lin Y, et al. GeniusRoute: a new analog routing paradigm using generative neural network guidance. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019

    Google Scholar 

  263. Xu B, Lin Y, Tang X, et al. WellGAN: generative-adversarial-network-guided well generation for analog/mixed-signal circuit layout. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2019. 1–6

    Google Scholar 

  264. Gusmão A, Horta N, Lourenço N, et al. Late breaking results: attention in Graph2Seq neural networks towards push-button analog IC placement. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2021. 1360–1361

    Google Scholar 

  265. Wang P C, Lin M P H, Liu C N J, et al. Layout synthesis of analog primitive cells with variational autoencoder. In: Proceedings of International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2023

    Google Scholar 

  266. Liu M, Zhu K, Gu J, et al. Towards decrypting the art of analog layout: placement quality prediction via transfer learning. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2020. 496–501

    Google Scholar 

  267. Lin Y, Li Y, Fang D, et al. Are analytical techniques worthwhile for analog IC placement? In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2022. 154–159

    Google Scholar 

  268. Xu P, Li J, Ho T Y, et al. Performance-driven analog layout automation: current status and future directions. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2024

    Google Scholar 

  269. Ren H, Kokai G F, Turner W J, et al. ParaGraph: layout parasitics and device parameter prediction using graph neural networks. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2020

    Google Scholar 

  270. Zhang Q, Su S, Liu J, et al. CEPA: CNN-based early performance assertion scheme for analog and mixed-signal circuit simulation. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020

    Google Scholar 

  271. Hakhamaneshi K, Werblun N, Abbeel P, et al. BagNet: Berkeley analog generator with layout optimizer boosted with deep neural networks. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019

    Google Scholar 

  272. Fang Y, Liu Z, Lu Y, et al. NPS: a framework for accurate program sampling using graph neural network. 2023. ArXiv:2304.08880

    Google Scholar 

  273. Li L, Flynn T, Hoisie A. Learning independent program and architecture representations for generalizable performance modeling. 2023. ArXiv:2310.16792

    Google Scholar 

  274. Yi X, Lu J, Xiong X, et al. Graph representation learning for microarchitecture design space exploration. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), 2023. 1–6

    Google Scholar 

  275. Sakhuja C, Shi Z, Lin C. Leveraging domain information for the efficient automated design of deep learning accelerators. In: Proceedings of IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023. 287–301

    Google Scholar 

  276. Shi Z, Zheng Z, Khan S, et al. DeepGate3: towards scalable circuit representation learning. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2024

    Google Scholar 

  277. Li M, Shi Z, Lai Q, et al. On EDA-driven learning for SAT solving. In: Proceedings of the 60th ACM/IEEE Design Automation Conference (DAC), 2023. 1–6

    Google Scholar 

  278. Shi Z, Li M, Khan S, et al. DeepTPI: test point insertion with deep reinforcement learning. In: Proceedings of IEEE International Test Conference (ITC), 2022. 194–203

    Google Scholar 

  279. Wang Z, Bai C, He Z, et al. Functionality matters in netlist representation learning. In: Proceedings of ACM/IEEE Design Automation Conference, 2022. 61–66

    Chapter  Google Scholar 

  280. Xie Z, Ren H, Khailany B, et al. PowerNet: transferable dynamic IR drop estimation via maximum convolutional neural network. In: Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 2020

    Google Scholar 

  281. Feng Z, Guo D, Tang D, et al. CodeBERT: a pre-trained model for programming and natural languages. 2020. ArXiv:2002.08155

    Google Scholar 

  282. Orenes-Vera M, Martonosi M, Wentzlaff D. From RTL to SVA: LLM-assisted generation of formal verification testbenches. 2023. ArXiv:2309.09437

    Google Scholar 

  283. Sorensson N, Een N. MiniSAT v1.13 - a SAT solver with conflict-clause minimization. SAT, 2005, 2005: 1–2

    Google Scholar 

  284. Fleury A, Heisinger M. CaDiCaL, Kissat, Paracooba, Plingeling and Treengeling entering the SAT competition 2020. SAT Competition, 2020, 2020: 50

    Google Scholar 

  285. Eén N, Mishchenko A, Sörensson N. Applying logic synthesis for speeding up SAT. In: Proceedings of Theory and Applications of Satisfiability Testing, 2007. 272–286

    Google Scholar 

  286. Akers S B. A truth table method for the synthesis of combinational logic. IRE Trans Electron Comput, 1961, EC-10: 604–615

    Article  Google Scholar 

  287. Zimmermann R, Tran D Q. Optimized synthesis of sum-of-products. In: Proceedings of the 37th Asilomar Conference on Signals, Systems & Computers, 2003. 867–872

    Google Scholar 

  288. Malik S, Wang A R, Brayton R K, et al. Logic verification using binary decision diagrams in a logic synthesis environment. In: Proceedings of IEEE International Conference on Computer-Aided Design, 1988. 6–7

    Google Scholar 

  289. Mishchenko A, Chatterjee S, Brayton R. Dag-aware aig rewriting a fresh look at combinational logic synthesis. In: Proceedings of the 43rd annual Design Automation Conference, 2006. 532–535

    Google Scholar 

  290. Zhang H T, Jiang J H R, Amarú L, et al. Deep integration of circuit simulator and SAT solver. In: Proceedings of the 58th ACM/IEEE Design Automation Conference (DAC), 2021. 877–882

    Google Scholar 

  291. Pan H, Lan C, Liu Y, et al. Physically aware synthesis revisited: guiding technology mapping with primitive logic gate placement. In: Proceedings of IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2024. 1–9

    Google Scholar 

  292. Zou S, Zhang J, Shi B, et al. BESWAC: boosting exact synthesis via wiser SAT solver call. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2024

    Google Scholar 

  293. Liu L, Fu B, Wong M D F, et al. Xplace: an extremely fast and extensible global placement framework. In: Proceedings of the 59th ACM/IEEE Design Automation Conference, 2022

    Google Scholar 

  294. Wang B, Shen G, Li D, et al. LHNN: lattice hypergraph neural network for VLSI congestion prediction. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2022

    Google Scholar 

  295. Pu Y, Shi C, Samson G, et al. A 9-mm2 ultra-low-power highly integrated 28-nm CMOS SoC for Internet of Things. IEEE J Solid-State Circ, 2018, 53: 936–948

    Article  Google Scholar 

  296. Jain S, Khare S, Yada S, et al. A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2012. 66–68

    Google Scholar 

  297. Klemme F, Amrouch H. Efficient learning strategies for machine learning-based characterization of aging-aware cell libraries. IEEE Trans Circ Syst I, 2022, 69: 5233–5246

    Google Scholar 

  298. Chowdhury A B, Tan B, Karri R, et al. OpenABC-D: a large-scale dataset for machine learning guided integrated circuit synthesis. 2021. ArXiv:2110.11292

    Google Scholar 

  299. Chai Z, Zhao Y, Liu W, et al. CircuitNet: an open-source dataset for machine learning in VLSI CAD applications with improved domain-specific evaluation metric and learning strategies. IEEE Trans Comput-Aided Des Integr Circ Syst, 2023, 42: 5034–5047

    Article  Google Scholar 

  300. Willsey M, Nandi C, Wang Y R, et al. egg: fast and extensible equality saturation. Proc ACM Program Lang, 2021, 5: 1–29

    Article  Google Scholar 

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Acknowledgements

This work was supported in part by Hong Kong S.A.R. General Research Fund (Grant No. 14212422) and Research Matching (Grant No. CSE-7-2022).

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Authors and Affiliations

  1. Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, 999077, China

    Tsung-Yi Ho, Sadaf Khan, Yu Li, Jinwei Liu, Yi Liu, Zhengyuan Shi, Ziyi Wang, Qiang Xu, Bei Yu, Evangeline F. Y. Young, Ziyang Zheng, Binwu Zhu & Keren Zhu

  2. School of Microelectronics, State Key Laboratory of Integrated Chips and System, Fudan University, Shanghai, 200433, China

    Hongyang Pan & Xuan Zeng

  3. Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, 999077, China

    Wenji Fang & Zhiyao Xie

  4. Huawei HiSilicon, Shenzhen, 518129, China

    Yu Huang

  5. Huawei Noah’s Ark Lab, Hong Kong, 999077, China

    Lei Chen, Min Li, Dimitrios Tsaras, Mingxuan Yuan & Hui-Ling Zhen

  6. Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, 315211, China

    Zhufei Chu

  7. School of Integrated Circuits, Peking University, Beijing, 100871, China

    Yiqi Chen, Ru Huang, Yun Liang, Yibo Lin, Guangyu Sun, Runsheng Wang, Chenhao Xue, Haoyi Zhang, Zuodong Zhang & Yuxiang Zhao

  8. School of Computer Science, Peking University, Beijing, 100871, China

    Guojie Luo, Xinming Wei & Sunan Zou

  9. Peng Cheng Laboratory, Shenzhen, 518052, China

    Xingquan Li

  10. School of Artificial Intelligence, Shanghai Jiao Tong University, Shanghai, 200240, China

    Junchi Yan

  11. School of Integrated Circuits, Southeast University, Nanjing, 210096, China

    Ru Huang & Jun Yang

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  1. Lei Chen
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Correspondence to Guojie Luo, Qiang Xu or Mingxuan Yuan.

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Cite this article

Chen, L., Chen, Y., Chu, Z. et al. Large circuit models: opportunities and challenges. Sci. China Inf. Sci. 67, 200402 (2024). https://doi.org/10.1007/s11432-024-4155-7

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  • Received: 22 April 2024

  • Revised: 19 July 2024

  • Accepted: 15 September 2024

  • Published: 25 September 2024

  • Version of record: 25 September 2024

  • DOI: https://doi.org/10.1007/s11432-024-4155-7

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Keywords

  • AI-rooted EDA
  • large circuit models (LCMs)
  • multimodal circuit representation learning
  • circuit optimization
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