这是indexloc提供的服务，不要输入任何密码
Skip to main content
Springer Nature Link
Log in

Mitigating methodology of hardware non-ideal characteristics for non-volatile memory based neural networks

  • Research Paper
  • Published:
Science China Information Sciences Aims and scope Submit manuscript

Abstract

Non-volatile memory-based computing-in-memory (nvCIM) paradigm has been extensively studied to boost the energy efficiency of neural network accelerators in edge applications. However, the degradation of inference accuracy induced by the non-ideal characteristics across circuits, arrays, and devices is becoming a crucial issue. In this work, we establish a hardware characteristic behavior model to analyze the impact of nvCIM non-ideal characteristics on neural network accuracy. Then we propose a hardware aware training and weight mapping correction methods to mitigate inference accuracy degradation. Through simulation verification, about 95% inference accuracy degradation is recovered by adopting the proposed mitigation method for various non-ideal characteristics and various neural network models. The feasibility of the proposed method is further proved in an experimental example with a flash-based LeNet recognition system.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+
from $39.99 /Month
  • Starting from 10 chapters or articles per month
  • Access and download chapters and articles from more than 300k books and 2,500 journals
  • Cancel anytime
View plans

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Explore related subjects

Discover the latest articles, books and news in related subjects, suggested using machine learning.

References

  1. Yao P, Wu H, Gao B, et al. Fully hardware-implemented memristor convolutional neural network. Nature, 2020, 577: 641–646

    Article  MATH  Google Scholar 

  2. Wan W, Kubendran R, Schaefer C, et al. A compute-in-memory chip based on resistive random-access memory. Nature, 2022, 608: 504–512

    Article  MATH  Google Scholar 

  3. Xue C X, Hung J M, Kao H Y, et al. A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2021. 245–247

    MATH  Google Scholar 

  4. Hung J M, Huang T H, Huang S P, et al. An 8-Mb DC-current-free binary-to-8b precision ReRAM nonvolatile computing-inmemory macro using time-space-readout with 1286.4-21.6 TOPS/W for edge-AI devices. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2022

    MATH  Google Scholar 

  5. Song S Y, Huang P, Shen W S, et al. A 3.3-Mbit/s true random number generator based on resistive random access memory. Sci China Inf Sci, 2023, 66: 219402

    Article  Google Scholar 

  6. Khaddam-Aljameh R, Stanisavljevic M, Fornt Mas J, et al. HERMES core-A 14nm CMOS and PCM-based in-memory compute core using an array of 300ps/LSB linearized CCO-based ADCs and local digital processing. In: Proceedings of Symposium on VLSI Circuits, 2021

    Google Scholar 

  7. Khwa W S, Chiu Y C, Jhang C J, et al. A 40-nm, 2M-Cell, 8b-precision, hybrid SLC-MLC PCM computing-in-memory Macro with 20.5–65.0 TOPS/W for tiny-Al edge devices. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2022

    MATH  Google Scholar 

  8. Chiu Y C, Yang C S, Teng S H, et al. A 22nm 4Mb STT-MRAM data-encrypted near-memory computation Macro with a 192GB/s read-and-decryption bandwidth and 25.1–55.1 TOPS/W 8b MAC for AI operations. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2022

    MATH  Google Scholar 

  9. Guo Z, Yin J, Bai Y, et al. Spintronics for energy-efficient computing: an overview and outlook. Proc IEEE, 2021, 109: 1398–1417

    Article  MATH  Google Scholar 

  10. Xiang Y C, Huang P, Yang H Z, et al. Storage reliability of multi-bit flash oriented to deep neural network. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2019

    MATH  Google Scholar 

  11. Zhang D, Wang H, Feng Y, et al. Implementation of image compression by using high-precision in-memory computing scheme based on NOR flash memory. IEEE Electron Dev Lett, 2021, 42: 1603–1606

    Article  MATH  Google Scholar 

  12. Yu G H, Huang P, Han R Z, et al. Co-optimization strategy between array operation and weight mapping for flash computing arrays to achieve high computing efficiency and accuracy. Sci China Inf Sci, 2023, 66: 129403

    Article  Google Scholar 

  13. Yang H Z, Huang P, Han R Z, et al. An ultra-high-density and energy-efficient content addressable memory design based on 3D-NAND flash. Sci China Inf Sci, 2023, 66: 142402

    Article  Google Scholar 

  14. Yayla M, Thomann S, Buschjager S, et al. Reliable binarized neural networks on unreliable beyond von-Neumann architecture. IEEE Trans Circ Syst I, 2022, 69: 2516–2528

    MATH  Google Scholar 

  15. Soliman T, Müller F, Kirchner T, et al. Ultra-low power flexible precision FeFET based analog in-memory computing. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2020

    MATH  Google Scholar 

  16. Jeong Y J, Zidan M A, Lu W D. Parasitic effect analysis in memristor-array-based neuromorphic systems. IEEE Trans Nanotechnol, 2018, 17: 184–193

    Article  MATH  Google Scholar 

  17. Chen L R, Li J W, Chen Y R, et al. Accelerator-friendly neural-network training: learning variations and defects in RRAM crossbar. In: Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017

    MATH  Google Scholar 

  18. Woo J, Moon K, Song J, et al. Improved synaptic behavior under identical pulses using AlOx/HfO2 bilayer RRAM array for neuromorphic systems. IEEE Electron Dev Lett, 2016, 37: 994–997

    Article  MATH  Google Scholar 

  19. Mao R, Wen B, Jiang M, et al. Experimentally-validated crossbar model for defect-aware training of neural networks. IEEE Trans Circ Syst II, 2022, 69: 2468–2472

    MATH  Google Scholar 

  20. Li H, Jiang Z, Huang P, et al. Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model. In: Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015

    MATH  Google Scholar 

  21. Xiang Y C, Huang P, Zhou Z, et al. Analog deep neural network based on nor flash computing array for high speed/energy efficiency computation. In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2019

    MATH  Google Scholar 

  22. Wu W, Wu H Q, Gao B, et al. A methodology to improve linearity of analog RRAM for neuromorphic computing. In: Proceedings of IEEE Symposium on VLSI Technology, 2018

    MATH  Google Scholar 

  23. Sun X, Yu S. Impact of non-ideal characteristics of resistive synaptic devices on implementing convolutional neural networks. IEEE J Emerg Sel Top Circ Syst, 2019, 9: 570–579

    Article  MATH  Google Scholar 

  24. Jain S, Sengupta A, Roy K, et al. RxNN: a framework for evaluating deep neural networks on resistive crossbars. IEEE Trans Comput-Aided Des Integr Circ Syst, 2021, 40: 326–338

    Article  MATH  Google Scholar 

  25. Peng X, Huang S, Jiang H, et al. DNN+NeuroSim V2.0: an end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training. IEEE Trans Comput-Aided Des Integr Circ Syst, 2021, 40: 2306–2319

    Article  MATH  Google Scholar 

  26. Zhu Z, Sun H, Xie T, et al. MNSIM 2.0: a behavior-level modeling tool for processing-in-memory architectures. IEEE Trans Comput-Aided Des Integr Circ Syst, 2023, 42: 4112–4125

    Article  MATH  Google Scholar 

  27. Chakraborty I, Ali M F, Kim D E, et al. GENIEx: a generalized approach to emulating non-ideality in memristive Xbars using neural networks. In: Proceedings of the 57th ACM/IEEE Design Automation Conference (DAC), 2020

    MATH  Google Scholar 

  28. Liu C C, Hu M, Strachan J P, et al. Rescuing memristor-based neuromorphic design with high defects. In: Proceedings of the 54th Annual Design Automation Conference, 2017

    MATH  Google Scholar 

  29. Yan B N, Yang J H, Wu Q, et al. A closed-loop design to enhance weight stability of memristor based neural network chips. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017

    MATH  Google Scholar 

  30. Liu B Y, Hu M, Li H, et al. Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine. In: Proceedings of the 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013

    MATH  Google Scholar 

  31. He Z Z, Lin J, Ewetz R, et al. Noise injection adaption: end-to-end ReRAM crossbar non-ideal effect adaption for neural network mapping. In: Proceedings of the 56th Annual Design Automation Conference, 2019

    MATH  Google Scholar 

  32. Chen P Y, Lin B B, Wang I T, et al. Mitigating effects of non-ideal synaptic device characteristics for on-chip learning. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015

    MATH  Google Scholar 

  33. Han L X, Xiang Y C, Huang P, et al. Novel weight mapping method for reliable NVM based neural network. In: Proceedings of IEEE International Reliability Physics Symposium (IRPS), 2021

    MATH  Google Scholar 

  34. Liao Y, Gao B, Yao P, et al. Diagonal matrix regression layer: training neural networks on resistive crossbars with interconnect resistance effect. IEEE Trans Comput-Aided Des Integr Circ Syst, 2021, 40: 1662–1671

    Article  MATH  Google Scholar 

  35. Sung C, Lim S, Kim H, et al. Effect of conductance linearity and multi-level cell characteristics of TaOx-based synapse device on pattern recognition accuracy of neuromorphic system. Nanotechnology, 2018, 29: 115203

    Article  MATH  Google Scholar 

  36. Liu P, You Z, Wu J, et al. Fault modeling and efficient testing of memristor-based memory. IEEE Trans Circ Syst I, 2021, 68: 4444–4455

    MATH  Google Scholar 

  37. Chen C Y, Shih H C, Wu C W, et al. RRAM defect modeling and failure analysis based on march test and a novel squeeze-search scheme. IEEE Trans Comput, 2015, 64: 180–190

    Article  MathSciNet  MATH  Google Scholar 

  38. Chen A. A comprehensive crossbar array model with solutions for line resistance and nonlinear device characteristics. IEEE Trans Electron Dev, 2013, 60: 1318–1326

    Article  MATH  Google Scholar 

  39. Han R Z, Huang P, Zhao Y D, et al. Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing. Sci China Inf Sci, 2019, 62: 22401

    Article  Google Scholar 

  40. Deng J, Dong W, Socher R, et al. ImageNet: a large-scale hierarchical image database. In: Proceedings of IEEE Conference on Computer Vision and Pattern Recognition, 2009

    MATH  Google Scholar 

  41. He K M, Zhang X Y, Ren S Q, et al. Deep residual learning for image recognition. In: Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2016

    MATH  Google Scholar 

  42. Vaswani A, Shazeer N, Parmar N, et al. Attention is all you need. In: Proceedings of the 31st International Conference on Neural Information Processing Systems, 2017

    MATH  Google Scholar 

Download references

Acknowledgements

This work was supported in part by National Key R&D Program of China (Grant No. 2023YFB4402405), National Natural Science Foundation of China (Grant Nos. 92064001, 62101018), 111 Project (Grant No. B18001), and Joint Funds of the National Natural Science Foundation of China (Grant No. U20A20204).

Author information

Authors and Affiliations

  1. School of Integrated Circuits, Peking University, Beijing, 100871, China

    Lixia Han, Peng Huang, Zheng Zhou, Haozhang Yang, Yiyang Chen, Xiaoyan Liu & Jinfeng Kang

  2. Beijing Advanced Innovation Center for Integrated Circuits, Beijing, 100871, China

    Lixia Han, Peng Huang, Zheng Zhou, Haozhang Yang, Yiyang Chen, Xiaoyan Liu & Jinfeng Kang

  3. School of Integrated Circuit Science and Engineering, Beihang University, Beijing, 100191, China

    Yijiao Wang

Authors
  1. Lixia Han
    View author publications

    Search author on:PubMed Google Scholar

  2. Peng Huang
    View author publications

    Search author on:PubMed Google Scholar

  3. Yijiao Wang
    View author publications

    Search author on:PubMed Google Scholar

  4. Zheng Zhou
    View author publications

    Search author on:PubMed Google Scholar

  5. Haozhang Yang
    View author publications

    Search author on:PubMed Google Scholar

  6. Yiyang Chen
    View author publications

    Search author on:PubMed Google Scholar

  7. Xiaoyan Liu
    View author publications

    Search author on:PubMed Google Scholar

  8. Jinfeng Kang
    View author publications

    Search author on:PubMed Google Scholar

Corresponding authors

Correspondence to Peng Huang or Yijiao Wang.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Han, L., Huang, P., Wang, Y. et al. Mitigating methodology of hardware non-ideal characteristics for non-volatile memory based neural networks. Sci. China Inf. Sci. 68, 122403 (2025). https://doi.org/10.1007/s11432-023-4021-y

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Version of record:

  • DOI: https://doi.org/10.1007/s11432-023-4021-y

Keywords