BibTeX record conf/fpga/ShaoLHL019

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@inproceedings{DBLP:conf/fpga/ShaoLHL019,
  author       = {Zhiyuan Shao and
                  Ruoshi Li and
                  Diqing Hu and
                  Xiaofei Liao and
                  Hai Jin},
  editor       = {Kia Bazargan and
                  Stephen Neuendorffer},
  title        = {Improving Performance of Graph Processing on {FPGA-DRAM} Platform
                  by Two-level Vertex Caching},
  booktitle    = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
                  Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
  pages        = {320--329},
  publisher    = {{ACM}},
  year         = {2019},
  url          = {https://doi.org/10.1145/3289602.3293900},
  doi          = {10.1145/3289602.3293900},
  timestamp    = {Sun, 19 Jan 2025 13:27:47 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/ShaoLHL019.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}