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Mohamed Hassan 0002
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Publications
- 2025
- [c29]Safin Bayes, Mohamed Hassan:
Criticality and Requirement Aware Heterogeneous Coherence for Mixed Criticality Systems. DATE 2025: 1-7 - 2024
- [j12]Mohamed Hossam, Salah Hessien, Mohamed Hassan:
Octopus: A Cycle-Accurate Cache System Simulator. IEEE Comput. Archit. Lett. 23(2): 191-194 (2024) - [c27]Safin Bayes, Mohamed Hossam, Mohamed Hassan:
Shared Data Kills Real-Time Cache Analysis. How to Resurrect It? DATE 2024: 1-6 - [c25]Bailian Sun, Mohamed Hassan:
HW/SW Collaborative Techniques for Accelerating TinyML Inference Time at No Cost. DSD 2024: 512-520 - 2023
- [j10]Salah Hessien
, Mohamed Hassan
PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems. ACM Trans. Embed. Comput. Syst. 22(1): 16:1-16:27 (2023) - [c23]Shorouk Abdelhalim, Danesh Germchi, Mohamed Hossam, Rodolfo Pellizzoni, Mohamed Hassan:
A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources. ECRTS 2023: 17:1-17:25 - [c20]Bailian Sun
The Case for tinyML in Healthcare: CNNs for Real-Time On-Edge Blood Pressure Estimation. SAC 2023: 629-638 - 2022
- [c19]Reza Mirosanlou, Mohamed Hassan
Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds. ECRTS 2022: 16:1-16:27 - [c18]Mohamed Hossam, Mohamed Hassan:
Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems. ECRTS 2022: 17:1-17:23 - 2021
- [j9]Anirudh Mohan Kaushik
Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems. IEEE Trans. Computers 70(12): 2098-2111 (2021) - [c16]Reza Mirosanlou, Mohamed Hassan
Duetto: Latency Guarantees at Minimal Performance Cost. DATE 2021: 1136-1141 - [c13]Reza Mirosanlou, Mohamed Hassan
DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance. MEMSYS 2021: 4:1-4:16 - 2020
- [j8]Reza Mirosanlou
MCsim: An Extensible DRAM Memory Controller Simulator. IEEE Comput. Archit. Lett. 19(2): 105-109 (2020) - [c11]Mohamed Hassan
Analysis of Memory-Contention in Heterogeneous COTS MPSoCs. ECRTS 2020: 23:1-23:24 - [c10]Reza Mirosanlou, Mohamed Hassan
DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining. RTAS 2020: 82-94 - [c9]Salah Hessien, Mohamed Hassan
The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications. RTSS 2020: 218-230 - 2019
- [c7]Nivedita Sritharan, Anirudh M. Kaushik, Mohamed Hassan
Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems. RTSS 2019: 433-445 - 2018
- [j5]Mohamed Hassan
MCXplore: Automating the Validation Process of DRAM Memory Controller Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1050-1063 (2018) - [j4]Mohamed Hassan
Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2323-2336 (2018) - [j3]Danlu Guo, Mohamed Hassan
A Comparative Study of Predictable DRAM Controllers. ACM Trans. Embed. Comput. Syst. 17(2): 53:1-53:23 (2018) - [j2]Mohamed Hassan
Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis. ACM Trans. Embed. Comput. Syst. 17(5): 90:1-90:25 (2018) - 2017
- [j1]Mohamed Hassan
PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems. ACM Trans. Embed. Comput. Syst. 16(4): 100:1-100:28 (2017) - [c5]Mohamed Hassan
Predictable Cache Coherence for Multi-core Real-Time Systems. RTAS 2017: 235-246 - [i1]Nivedita Sritharan, Anirudh M. Kaushik, Mohamed Hassan, Hiren D. Patel:
HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems. CoRR abs/1706.07568 (2017) - 2016
- [c4]Mohamed Hassan, Hiren D. Patel:
MCXplore: An automated framework for validating memory controller designs. DATE 2016: 1357-1362 - [c3]Mohamed Hassan
Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems. RTAS 2016: 73-83 - 2015
- [c2]Mohamed Hassan
Reverse-engineering embedded memory controllers through latency-based analysis. RTAS 2015: 297-306 - [c1]Mohamed Hassan
A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems. RTAS 2015: 307-316
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