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Xinmiao Zhang 0001
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Publications
- 2025
- [j69]Xinmiao Zhang
, Chongyan Gu, Mengmei Ye, Qiang Liu, Reza Azarderakhsh, Weiqiang Liu, Yang Li:
Guest Editorial Special Issue on Emerging Hardware Security and Trust Technologies - AsianHOST 2023. IEEE Trans. Circuits Syst. I Regul. Pap. 72(2): 482 (2025) - 2024
- [j60]Jiafeng Xie
Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1670-1676 (2024) - 2023
- [j57]Tuvi Etzion, Paul H. Siegel
Dimensions of Channel Coding: From Theory to Algorithms to Applications. IEEE J. Sel. Areas Inf. Theory 4: v-xiii (2023) - [j56]Weihang Tan
High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography. IEEE Trans. Computers 72(9): 2454-2466 (2023) - [j55]Jingbo Zhou
Algorithmic Obfuscation for LDPC Decoders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 371-383 (2023) - [j54]Jingbo Zhou
Joint Protection Scheme for Deep Neural Network Hardware Accelerators and Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4518-4527 (2023) - 2022
- [j46]Xinmiao Zhang
Polynomial Multiplication Architecture with Integrated Modular Reduction for R-LWE Cryptosystems. J. Signal Process. Syst. 94(8): 799-809 (2022) - [j45]Zheang Huai
Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime. J. Signal Process. Syst. 94(10): 1067-1082 (2022) - [c64]Jingbo Zhou, Elsayed Elgendy, Eslam Yahya Tawfik, Xinmiao Zhang:
Low-Complexity AES Architectures Resilient to Power Analysis Attacks. ISCAS 2022: 165-169 - [i5]Jingbo Zhou, Xinmiao Zhang:
Joint Protection Scheme for Deep Neural Network Hardware Accelerators and Models. CoRR abs/2210.03249 (2022) - 2021
- [j43]Deepu John
Special Section on Edge AI and Accelerators. IEEE Open J. Circuits Syst. 2: 128-130 (2021) - [j41]Jingbo Zhou
Generalized SAT-Attack-Resistant Logic Locking. IEEE Trans. Inf. Forensics Secur. 16: 2581-2592 (2021) - [c60]Weihang Tan, Antian Wang
Pipelined High-Throughput NTT Architecture for Lattice-Based Cryptography. AsianHOST 2021: 1-4 - [c59]Xinmiao Zhang, Keshab K. Parhi
Reduced-Complexity Modular Polynomial Multiplication for R-LWE Cryptosystems. ICASSP 2021: 7853-7857 - [c56]Jingbo Zhou, Xinmiao Zhang:
A Low-Complexity Flexible Logic-Locking Scheme Resisting Removal Attacks. MWSCAS 2021: 869-873 - [c55]Zheang Huai
Efficient Architecture for Long Integer Modular Multiplication over Solinas Prime. SiPS 2021: 146-151 - [i4]Jingbo Zhou, Xinmiao Zhang:
Algorithmic Obfuscation for LDPC Decoders. CoRR abs/2104.03814 (2021) - [i3]Weihang Tan, Antian Wang, Yingjie Lao, Xinmiao Zhang, Keshab K. Parhi:
Low-Latency VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography. CoRR abs/2110.12127 (2021) - 2020
- [c51]Jingbo Zhou, Xinmiao Zhang:
A New Logic-Locking Scheme Resilient to Gate Removal Attack. ISCAS 2020: 1-5 - 2019
- [j35]Xinmiao Zhang
On the Construction of Composite Finite Fields for Hardware Obfuscation. IEEE Trans. Computers 68(9): 1353-1364 (2019) - [c47]Ankur A Sharma, Xinmiao Zhang, Yingjie Lao:
Hardware Obfuscation Through Reconfiguration Finite Field Arithmetic Units. ISCAS 2019: 1-5 - [c46]Xinmiao Zhang, Phillip Shvartsman, Jingbo Zhou, Eslam Yahya Tawfik:
Hardware Obfuscation of AES through Finite Field Construction Variation. ISCAS 2019: 1-5 - [c43]Phillip Shvartsman, Xinmiao Zhang:
Side Channel Attack Resistant AES Design Based on Finite Field Construction Variation. SiPS 2019: 67-72 - [i2]Jingbo Zhou, Xinmiao Zhang:
Generalized SAT-Attack-Resistant Logic Locking. CoRR abs/1910.12142 (2019) - 2014
- [j27]Fang Cai, Xinmiao Zhang, David Declercq, Shiva Kumar Planjery, Bane Vasic:
Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1366-1375 (2014) - [j26]Fang Cai, Xinmiao Zhang:
Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation. J. Signal Process. Syst. 76(2): 211-222 (2014) - 2013
- [j24]Xinmiao Zhang, Yu Zheng:
Generalized Backward Interpolation for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Commun. 61(1): 13-23 (2013) - [j23]Fang Cai, Xinmiao Zhang:
Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2010-2023 (2013) - [c36]Xinmiao Zhang, Fang Cai, M. P. Anantram:
Low-energy and low-latency error-correction for phase change memory. ISCAS 2013: 1236-1239 - [c35]Fang Cai, Xinmiao Zhang, David Declercq, Bane Vasic, Dung Viet Nguyen, Shiva Kumar Planjery:
Low-complexity finite alphabet iterative decoders for LDPC codes. ISCAS 2013: 1332-1335 - [c34]Wei Zhang, Jing Wang, Xinmiao Zhang:
Low-power design of Reed-Solomon encoders. ISCAS 2013: 1560-1563 - [c33]Xinmiao Zhang, Richard Shi, James A. Ritcey:
Reducing the latency of Lee-O'Sullivan interpolation through modified initialization. ITA 2013: 1-5 - 2012
- [j22]Xinmiao Zhang, Jiangli Zhu, Wei Zhang:
Efficient Reencoder Architectures for Algebraic Soft-Decision Reed-Solomon Decoding. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 163-167 (2012) - [j21]Xinmiao Zhang, Yu Zheng:
Systematically Re-encoded Algebraic Soft-Decision Reed-Solomon Decoder. IEEE Trans. Circuits Syst. II Express Briefs 59-II(6): 376-380 (2012) - [j20]Xinmiao Zhang, Zhongfeng Wang:
A Low-Complexity Three-Error-Correcting BCH Decoder for Optical Transport Network. IEEE Trans. Circuits Syst. II Express Briefs 59-II(10): 663-667 (2012) - [j19]Xinmiao Zhang, Yingquan Wu, Jiangli Zhu, Yu Zheng:
Novel Interpolation and Polynomial Selection for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1318-1322 (2012) - [j18]Xinmiao Zhang, Fang Cai, Shu Lin:
Low-Complexity Reliability-Based Message-Passing Decoder Architectures for Non-Binary LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1938-1950 (2012) - [j17]Xinmiao Zhang, Jiangli Zhu, Wei Zhang:
Modified Low-Complexity Chase Soft-Decision Decoder of Reed-Solomon Codes. J. Signal Process. Syst. 66(1): 3-13 (2012) - [j16]Jiangli Zhu, Xinmiao Zhang:
Efficient Generalized Minimum-distance Decoders of Reed-Solomon Codes. J. Signal Process. Syst. 66(3): 245-257 (2012) - [c32]Wei Zhang, Xinmiao Zhang, Hao Wang:
Increasing the energy efficiency of WSNs using algebraic soft-decision reed-solomon decoders. APCCAS 2012: 49-52 - [c31]Xinmiao Zhang, Yu Zheng, Yingquan Wu:
A Chase-type Koetter-Vardy algorithm for soft-decision Reed-Solomon decoding. ICNC 2012: 466-470 - [c29]Xinmiao Zhang, Fang Cai, Richard Shi:
Low-power LDPC decoding based on iteration prediction. ISCAS 2012: 3041-3044 - [c27]Xinmiao Zhang, Richard Shi, James A. Ritcey:
On the implementation of modified fuzzy vault for biometric encryption. ITA 2012: 56-61 - [c26]Fang Cai, Xinmiao Zhang:
Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation. SiPS 2012: 137-142 - [i1]Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang:
Reduced-Complexity Column-Layered Decoding and Implementation for LDPC Codes. CoRR abs/1204.2577 (2012) - 2011
- [j15]Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang:
Reduced-complexity column-layered decoding and implementation for LDPC codes. IET Commun. 5(15): 2177-2186 (2011) - [j14]Somnath Paul, Fang Cai, Xinmiao Zhang, Swarup Bhunia
Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache. IEEE Trans. Computers 60(1): 20-34 (2011) - [j13]Xinmiao Zhang, Fang Cai:
Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(2): 402-414 (2011) - [j12]Xinmiao Zhang, Fang Cai:
Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1229-1238 (2011) - [c25]Xinmiao Zhang, Fang Cai:
An efficient architecture for iterative soft reliability-based majority-logic non-binary LDPC decoding. ACSCC 2011: 885-888 - [c24]Xinmiao Zhang, Fang Cai:
Low-complexity architectures for reliability-based message-passing non-binary LDPC decoding. ISCAS 2011: 1303-1306 - [c23]Xinmiao Zhang, Yingquan Wu, Jiangli Zhu:
A novel polynomial selection scheme for low-complexity chase algebraic soft-decision reed-solomon decoding. ISCAS 2011: 2689-2692 - [c22]Xinmiao Zhang, Yu Zheng:
Efficient codeword recovery architecture for low-complexity Chase Reed-Solomon decoding. ITA 2011: 510-513 - 2010
- [j11]Xinmiao Zhang, Jiangli Zhu:
High-Throughput Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(3): 581-591 (2010) - [j10]Xinmiao Zhang, Jiangli Zhu:
Algebraic Soft-Decision Decoder Architectures for Long Reed-Solomon Codes. IEEE Trans. Circuits Syst. II Express Briefs 57-II(10): 787-792 (2010) - [c21]Xinmiao Zhang, Fang Cai:
Reduced-latency scheduling scheme for min-max non-binary LDPC decoding. APCCAS 2010: 414-417 - [c20]Jiangli Zhu, Xinmiao Zhang:
Efficient architecture for generalized minimum-distance decoder of Reed-Solomon codes. ICASSP 2010: 1502-1505 - [c19]Xinmiao Zhang, Fang Cai:
Partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes. ICASSP 2010: 1506-1509 - [c17]Jiangli Zhu, Xinmiao Zhang:
High-speed re-encoder design for algebraic soft-decision Reed-Solomon decoding. ISCAS 2010: 465-468 - [c16]Xinmiao Zhang, Jiangli Zhu:
Hardware complexities of algebraic soft-decision Reed-Solomon decoders and comparisons. ITA 2010: 558-567 - 2009
- [j9]Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang:
Backward Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding. IEEE Trans. Very Large Scale Integr. Syst. 17(11): 1602-1615 (2009) - [c15]Jiangli Zhu, Xinmiao Zhang:
Factorization-free Low-complexity Chase Soft-decision Decoding of Reed-Solomon Codes. ISCAS 2009: 2677-2680 - 2008
- [j8]Jiangli Zhu, Xinmiao Zhang:
Efficient VLSI Architecture for Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(10): 3050-3062 (2008) - [c13]Jiangli Zhu, Xinmiao Zhang:
Scalable interpolation architecture for soft-decision Reed-Solomon decoding. APCCAS 2008: 41-44 - [c12]Qingwei Li, Zhongfeng Wang, Xinmiao Zhang, Xingcheng Liu
Efficient architecture for the Tate pairing in characteristic three. APCCAS 2008: 1111-1115 - [c11]Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang, Qingwei Jia:
Efficient decoder design for high-throughput LDPC decoding. APCCAS 2008: 1640-1643 - [c10]Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang:
Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes. ICCD 2008: 526-531 - [c9]Bainan Chen, Xinmiao Zhang:
FPGA implementation of a factorization processor for soft-decision reed-solomon decoding. ISCAS 2008: 944-947 - [c8]Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang:
Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes. ISCAS 2008: 3078-3081 - [c7]Xinmiao Zhang, Jiangli Zhu:
Efficient interpolration architecture for soft-decision Reed-Solomon decoding by applying slow-down. SiPS 2008: 19-24 - [c6]Bainan Chen, Xinmiao Zhang, Zhongfeng Wang:
Error correction for multi-level NAND flash memory using Reed-Solomon codes. SiPS 2008: 94-99 - 2007
- [j7]Nicolas Sklavos
MONET Special Issue on Next Generation Hardware Architectures for Secure Mobile Computing. Mob. Networks Appl. 12(4): 229-230 (2007) - [c5]Xinmiao Zhang, Jiangli Zhu:
Low-complexity Interpolation Architecture for Soft-decision Reed-Solomon Decoding. ISCAS 2007: 1413-1416 - [c4]Jiangli Zhu, Xinmiao Zhang:
Efficient Interpolation Architecture for Soft-Decision Reed-Solomon Decoding. SiPS 2007: 663-668 - 2006
- [j5]Xinmiao Zhang, Keshab K. Parhi
On the Optimum Constructions of Composite Field for the AES Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1153-1157 (2006) - 2005
- [j3]Xinmiao Zhang, Keshab K. Parhi
Fast factorization architecture in soft-decision Reed-Solomon decoding. IEEE Trans. Very Large Scale Integr. Syst. 13(4): 413-426 (2005) - [j2]Xinmiao Zhang, Keshab K. Parhi
High-Speed Architectures for Parallel Long BCH Encoders. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 872-877 (2005) - 2004
- [j1]Xinmiao Zhang, Keshab K. Parhi
High-speed VLSI architectures for the AES algorithm. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 957-967 (2004) - [c1]Xinmiao Zhang, Keshab K. Parhi
High-speed architectures for parallel long BCH encoders. ACM Great Lakes Symposium on VLSI 2004: 1-6
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