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Brucek Khailany
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Publications
- 2023
- [j13]Haoxing Ren
, Brucek Khailany
Machine Learning and Algorithms: Let Us Team Up for EDA. IEEE Des. Test 40(1): 70-76 (2023) - [c53]Chia-Tung Ho
NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model. ISPD 2023: 44-52 - 2021
- [j10]Yakun Sophia Shao, Jason Clemons
Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM 64(6): 107-116 (2021) - [i5]Haoxing Ren, Matthew Fojtik, Brucek Khailany:
NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning. CoRR abs/2107.07044 (2021) - 2020
- [j8]Brian Zimmer
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits 55(4): 920-932 (2020) - 2019
- [c28]Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany:
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. ASYNC 2019: 27-35 - [c23]Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium 2019: 1-24 - [c22]Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang
MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD 2019: 1-8 - [c20]Yakun Sophia Shao, Jason Clemons
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO 2019: 14-27 - [c19]Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits 2019: 300- - 2018
- [c18]Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons
A modular digital VLSI flow for high-productivity SoC design. DAC 2018: 72:1-72:6 - 2016
- [c15]Divya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun:
Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks. ASYNC 2016: 75-82 - 2015
- [c13]Ben Keller, Matthew Fojtik, Brucek Khailany:
A Pausible Bisynchronous FIFO for GALS Systems. ASYNC 2015: 1-8
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