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Brucek Khailany
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Publications
- 2025
- [i23]Nathaniel Ross Pinckney, Chenhui Deng, Chia-Tung Ho, Yun-Da Tsai, Mingjie Liu, Wenfei Zhou, Brucek Khailany, Haoxing Ren:
Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification. CoRR abs/2506.14074 (2025) - 2024
- [c60]Christopher Batten
, Nathaniel Ross Pinckney
PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs. MLCAD 2024: 10:1-10:17 - [i19]Nathaniel Ross Pinckney, Christopher Batten, Mingjie Liu, Haoxing Ren, Brucek Khailany:
Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks. CoRR abs/2408.11053 (2024) - 2023
- [c57]Rongjian Liang
Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation. DAC 2023: 1-2 - [c55]Mingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, Haoxing Ren:
Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation. ICCAD 2023: 1-8 - [i17]Mingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, Haoxing Ren:
VerilogEval: Evaluating Large Language Models for Verilog Code Generation. CoRR abs/2309.07544 (2023) - [i16]Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Ross Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany, Kishor Kunal, Xiaowei Li, Hao Liu, Stuart F. Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raiman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P. Suthar, Varun Tej, Kaizhe Xu, Haoxing Ren:
ChipNeMo: Domain-Adapted LLMs for Chip Design. CoRR abs/2311.00176 (2023) - 2021
- [j10]Yakun Sophia Shao, Jason Clemons
Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM 64(6): 107-116 (2021) - [c38]Nathaniel Ross Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany:
IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs. ICCAD 2021: 1-9 - [i8]Steve Dai, Alicia Klinefelter, Haoxing Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Ross Pinckney, Brucek Khailany:
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking. CoRR abs/2102.06326 (2021) - 2020
- [j8]Brian Zimmer
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits 55(4): 920-932 (2020) - 2019
- [c28]Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany:
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. ASYNC 2019: 27-35 - [c23]Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium 2019: 1-24 - [c22]Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang
MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD 2019: 1-8 - [c20]Yakun Sophia Shao, Jason Clemons
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO 2019: 14-27 - [c19]Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits 2019: 300- - 2018
- [c18]Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons
A modular digital VLSI flow for high-productivity SoC design. DAC 2018: 72:1-72:6
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last updated on 2025-11-09 23:22 CET by the dblp team
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