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Jing Jin 0005

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Li Ding

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Publications

2022
[j19]
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  - journals/ieiceta/DingJZ22
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  persistent URL:
  - https://dblp.org/rec/journals/ieiceta/DingJZ22
Li Ding, Jing Jin, Jianjun Zhou:
A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(11): 1443-1449 (2022)
2021
[j12]
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  - journals/mj/DingWJZ21
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  - https://dblp.org/rec/journals/mj/DingWJZ21
Li Ding, Ke Wu, Jing Jin, Jianjun Zhou:
An 8 GHz real-time temperature-compensated PLL with 20.8 ppm/°C temperature coefficient for SerDes applications. Microelectron. J. 117: 105279 (2021)
2019
[c16]
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  dblp key:
  - conf/asicon/GuoDJ19
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  - https://dblp.org/rec/conf/asicon/GuoDJ19
Songhao Guo, Li Ding, Jing Jin:
A 16/32Gb/s NRZ/PAM4 Receiver with Dual-Loop CDR and Threshold Voltage Calibration. ASICON 2019: 1-4
[c15]
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  - conf/asicon/JiDJ19
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Yu Ji, Li Ding, Jing Jin:
A High-Linear Digital-to-Phase Converter in 40nm CMOS. ASICON 2019: 1-4
2018
[c11]
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  dblp key:
  - conf/iscas/LiuDJZ18
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  - https://dblp.org/rec/conf/iscas/LiuDJZ18
Heng Liu, Li Ding, Jing Jin, Jianjun Zhou:
A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse. ISCAS 2018: 1-5
[c10]
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  dblp key:
  - conf/iscas/TangDJZ18
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  - https://dblp.org/rec/conf/iscas/TangDJZ18
Hanchun Tang, Li Ding, Jing Jin, Jianjun Zhou:
A 28 Gb/s 2-Tap FFE Source-Series-Terminated Transmitter in 22 nm CMOS FDSOI. ISCAS 2018: 1-4

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