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15th SMACD 2018: Prague, Czech Republic
- 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018, Prague, Czech Republic, July 2-5, 2018. IEEE 2018, ISBN 978-1-5386-5153-7
- Luis Gerardo de la Fraga, Esteban Tlelo-Cuautle
:
Linearizing the Transconductance of an OTA Through the Optimal Sizing by Applying NSGA-II. 1-9 - Gian Carlo Cardarilli, Luca Di Nunzio
Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker. 1-20 - Andreas Herrmann, Michael Weiner, Michael Pehl, Helmut Graeb:
Bringing Analog Design Tools to Security: Modeling and Optimization of a Low Area Probing Detector. 1-4 - Danhui Li, Delong Shang, Fei Xia, Alex Yakovlev:
Modelling Switched-Capacitor DC-DC Converters with Signal Transition Graphs. 1-100 - Fábio Passos
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs. 1-164 - Giulia Di Capua
Loss Behavioral Modeling for Ferrite Inductors. 1-9 - Ezgi Kaya
An Analog/RF Circuit Synthesis and Design Assistant Tool for Analog IP: DATA-IP. 1-9 - Antonio Toro-Frías, Pablo Martín-Lloret, Javier Martín-Martínez, Rafael Castro-López
Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs. 1-9 - António Canelas, Ricardo Povoa
A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications. 1-4 - Kateryna Stoyka, Ricieri Akihito Pessinatti Ohashi, Nicola Femia:
Behavioral Switching Loss Modeling of Inverter Modules. 1-120 - Maike Taddiken, Theodor Hillebrand, Steffen Paul, Dagmar Peters-Drolshagen:
LUT-Based Stochastic Modeling for Non-Normal Performance Distributions. 1-217 - Mohammed A. Almoteriy, Mohamed I. Sobhy, John C. Batchelor
Antenna Modeling Technique for Digital Communication Systems. 1-48 - Marcel Urban, Sachin S. Sapatnekar, Richard Shi:
Plenaries. 1-2 - Christine Forster, Jérôme Kirscher, Linus Maurer
Metamodel-Based Performance Evaluation for an Electromechanical Automotive System. 1-9 - Min Soo Bae, Chuntaek Park, Ilgu Yun:
Compact Drain Current Model of Nanoscale FinFET Considering Short Channel Effect in Ballistic Transport Regime. 1-112 - Wieslaw Marszalek
2D Bifurcations and Chaos in Nonlinear Circuits: a Parallel Computational Approach. 1-300 - Sarah Azimi
SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs. 1-52 - Chase Cook, Sheriff Sadiqbatcha, Zeyu Sun, Sheldon X.-D. Tan:
Reliability Based Hardware Trojan Design Using Physics-Based Electromigration Models. 5-8 - Giovanni Piccinni
Analysis and Modeling of a Novel SDR-Based High-Precision Positioning System. 13-16 - Sheriff Sadiqbatcha, Chase Cook, Zeyu Sun, Sheldon X.-D. Tan:
Accelerating Electromigration Wear-Out Effects Based on Configurable Sink-Structured Wires. 21-24 - Engin Afacan, Yigit Ender Avci, Omer Osman Demirbas:
Variability Analysis Tool for CMOS Analog/RF Circuits: VariAnT. 25-28 - Pablo Saraza-Canflanca
Automated Massive RTN Characterization Using a Transistor Array Chip. 29-32 - Giuseppe Fontana
Testability Analysis Based on Complex-Field Fault Modeling. 33-36 - Pietro Burrascano, Stefano Laureti
The Reactance Transformation for Near Sidelobes Reduction: A Comparison of Windowing Techniques. 37-40 - Javier Diaz-Fortuny
A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation. 53-56 - Hussam Amrouch
Voltage Adaptation Under Temperature Variation. 57-60 - Theodor Hillebrand, Maike Taddiken, Steffen Paul, Dagmar Peters-Drolshagen:
Yield Approximation of Analog Integrated Circuits Under Time-Dependent Variability. 65-68 - Mohammad Saber Golanbari, Mehdi Baradaran Tahoori:
Optimizing Datapaths for Near Threshold Computing. 69-72 - Pablo Saraza-Canflanca
Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models. 73-76 - Sadik Ilik, Fikret Basar Gencer, Mustafa Berke Yelten:
Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT). 77-80 - Hector J. Quintero, Manuel Jiménez Través
Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. 81-84 - Abubaker Sasi, Amirali Amirsoleimani, Majid Ahmadi, Arash Ahmadi:
A Memristive TaOx-Based Median Filter Design for Image Processing Application. 85-88 - Marta Franceschi
Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation. 89-92 - Tuba Ayhan, Mustafa Altun
Approximate Fully Connected Neural Network Generation. 93-96 - Ramin Khayatzadeh, Mustafa Berke Yelten:
A Novel Multiple Membership Function Generator for Fuzzy Logic Systems. 101-104 - Nihat Akkan, Mustafa Altun
Parameter Extraction Method Using Hybrid Artificial Bee Colony Algorithm for an OFET Compact Model. 105-108 - Maria-Alexandra Paun, Catherine Dehollain:
Three-Dimensional Modeling of Insulin Pen for Multi-Electrode Capacitive Sensing. 113-116 - Nina Parkalian, Markus Robens, Christian Grewing, Volker Christ, Dennis Liebau, P. Muralidharan, Dennis Nielinger, Ugur Yegin, Andre Zambanini, Stefan van Waasen:
Modeling and Simulation of Digital Phase-Locked Loop in Simulink. 121-9 - Engin Afacan, Günhan Dündar
Design Space Exploration of CMOS Cross-Coupled LC Oscillators via RF Circuit Synthesis. 125-128 - Ricardo Martins
Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications. 129-132 - Nuno Lourenço
On the Exploration of Promising Analog IC Designs via Artificial Neural Networks. 133-136 - Nawel Drira, Mouna Kotti, Mourad Fakhfakh, Patrick Siarry, Esteban Tlelo-Cuautle
Expected Improvement-Based Optimization Approach for the Optimal Sizing of a CMOS Operational Transconductance Amplifier. 137-9 - Vadim Borisov, Jürgen Scheible:
Lithography Hotspots Detection Using Deep Learning. 145-148 - Georg Gläser, Martin Grabmann, Dirk Nuernbergk:
Impact Rating of Layout Parasitics in Mixed-Signal Circuits: Finding a Needle in a Haystack. 149-152 - Umberto Garlando, Fabrizio Riente
ToPoliNano & MagCAD: A Complete Framework for Design and Simulation of Digital Circuits Based on Emerging Technologies. 153-156 - Maike Taddiken, Steffen Paul, Dagmar Peters-Drolshagen:
ReSeMBleD-Methods for Response Surface Model Behavioral Description. 157-160 - Abhaya Chandra Kammara, Andreas König:
Absynth: A Comprehensive Approach for Full Front to Back Analog Design Automation. 165-168 - Hsin-Ju Hsu, Wan-Chun Chen, Long-Ching Yeh, Chien-Nan Jimmy Liu:
Spec-to-Layout Automation Flow for Buck Converters with Current-Mode Control in SOC Applications. 169-172 - Guan-Hong Liou, Shuo-Hui Wang, Yan-Yu Su, Mark Po-Hung Lin
Classifying Analog and Digital Circuits with Machine Learning Techniques Toward Mixed-Signal Design Automation. 173-176 - Islam Nashaat, Inas Mohammed, Mohamed Dessouky, Hazem Said:
Mismatch-Aware Placement of Device Arrays Using Genetic Optimization. 177-180 - Po-Cheng Pan, Hung-Wen Huang, Chien-Chia Huang, Abhishek Patyal, Hung-Ming Chen, Tsun-Yu Yang:
On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts. 181-184 - Ahmed M. Saied, M. M. Abutaleb
Analytical Method for Ultra-Low Power UWB Low-Noise Amplifiers. 189-192 - Aleksandar Pajkanovic
Temperature Performance of Meander-Type Inductor in Silicon Technology. 193-196 - Johannes Herrmann, David Bierbuesse, Renato Negra:
Universal Model for Millimeter-Wave Integrated Transformers. 197-200 - Charalampos Antoniadis
On the Sparsification of the Reluctance Matrix in RLCk Circuit Transient Analysis. 201-204 - George Floros
Efficient Hotspot Thermal Simulation Via Low-Rank Model Order Reduction. 205-208 - Dimitrios Garyfallou
A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit Simulation on GPU s. 209-212 - Jennifer Freeley, Dmytro Mishagli, Tom Brazil, Elena Blokhina
Statistical Simulations of Delay Propagation in Large Scale Circuits Using Graph Traversal and Kernel Function Decomposition. 213-9 - Fabian Speicher, Jonas Meier, Christoph Beyerstedt, Ralf Wunderlich, Stefan Heinen:
Advanced Modeling Methodology for Expedient RF SoC Verification and Performance Estimation. 221-224 - Eva Schmidt, Thomas Dürbaum:
Fast Converter Simulation Method Including Parasitic Nonlinear Capacitances. 225-228 - Pietro Burrascano, Giulia Di Capua
Pulse Compression for Ferrite Inductors Modeling in Moderate Saturation. 229-232 - Alberto Oliveri
Accurate Modeling of Inductors Working in Nonlinear Region in Switch-Mode Power Supplies with Different Load Currents. 233-236 - Daniele Scirè
A Temperature Dependent Non-Linear Inductor Model for a DC/DC Boost Converter. 237-9 - Giulia Di Capua
Geometric form Factors-Based Power Transformers Design. 245-248 - Elisa Sacco
Controlled-Oscillator Optimization for Highly-Digital CMOS Time-Based Sensor-to-Digital Converter Architectures. 249-252 - Alessandro Catania
Analysis and Simulation of Chopper Stabilization Techniques Applied to Delta-Sigma Converters. 253-256 - Roman Sotner
New Reconfigurable Universal SISO Biquad Filter Implemented by Advanced CMOS Active Elements. 257-260 - Karel Hajek
System of Standard Approximations for Optimum Frequency Filter Design. 261-264 - Jiri Vavra
Design and Error Analysis of Inductance Multiplier via Symbolic Algorithms. 265-268 - Ahmad Mohammadi, Mohammad Chahardori:
A Low-Power, Bootstrapped Sample and Hold Circuit with Extended Input Ranged for Analog-to-Digital Converters in CMOS 0.18 μm. 269-272 - Cheng-En Lee, Shi-Yu Huang:
A Cell-Based Fractional-N Phase-Locked Loop Compiler. 273-276 - Weiwei Shi, An Pan:
Mixed Design of SPAD Array Based TOF for Depth Camera and Unmanned Vehicle Applications. 277-280 - Muhammad Riaz ur Rehman, Nabeel Ahmad
Modeling of Reference Injection Based Low-Power All-Digital Phase-Locked Loop for Bluetooth Low-Energy Applications in Lab VIEW. 281-283 - Jiri Nahlik, Jirí Hospodka, Ondrej Subrt:
SC Filter Optimization Performance by Hybrid Simplex Algorithm. 285-288 - Chee Young Lee, Chae Won Kim, Hyejin Im, Soo Youn Kim, Minkyu Song:
A Low Power Priority Encoding Technique with Address-Encoder and Reset-Decoder for an Improved Hierarchical Asynchronous Detector. 289-292 - Mouna Kotti, Mourad Fakhfakh, Esteban Tlelo-Cuautle
Kriging Metamodeling-Assisted Multi-Objective Optimization of CMOS Current Conveyors. 293-296 - Vicente Yair Ponce-Hinestroza, Victor R. Gonzalez-Diaz:
System-Level Behavioral Model of a 12-Bit 1.5-Bit Per Stage Pipelined ADC Based on Verilog®=-AMS. 301-304 - Cristian E. Onete
Reconfiguring Passive Linear Circuits. 305-308
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